What's the use of U14 (dual PNP transistors) around P-FET?

[jwatte]

In the HAT specifiction, this diagram is shown:
https://github.com/raspberrypi/hats/blo ... ircuit.png

I have previously only seen and used the "ideal diode" implemented with a single low-Rdson P-channel MOSFET and a weak resistor to ground.

What is the use of the pair of PNP transistors (U14) in this diagram?

[Tage]

I think the circuit is controlling the gate voltage ( by controlling the current flow in the 47k resistor) in the way that the p-channel MOSFET is on if Drain is higher than Source (there is a forward voltage on the body diode of the MOSFET), and it turns off if Source is higher than Drain (body diode is reverse biased).

[jwatte]

Oh, I see! The idea is to provide a diode even when both Vin and Vout are kept above GND. I've only seen the variant used as reverse-power-accident-prevention before, which doesn't need any of the extra components -- a single P-MOSFET is enough (perhaps with a Zener and resistor if you expect significant overvoltage compared the Vgsmax.)

Also, isn't the arrow mis-labeled? The MOSFET would allow a positive voltage in the direction of the arrow; it would drive voltage towards zero in the reverse direction (forward for the "diode.") Shouldn't it say "~0 mA" the direction it's currently pointing?

[mahjongg]

The transistors are wired in a "current mirror/comparator" configuration, and they make sure the FET is turned on at the right time, then the the diode drop of the inherent diode in the FET is shortened, so there is no "forward" voltage, and the circuit becomes an "ideal diode".

When the inherent diode is blocking, then the FET is also turned off.

also read: http://www.raspberrypi.org/forums/viewt ... 1f#p579819

[BudBennett]

It is a closed loop unity-gain AMPLIFIER, with an offset. I am uncertain about the true schematic values because the Adafruit schematic shows both resistors as 10k, but the GitHub schematic has the bias resistor, R2, as 10K, and the load resistor, R3, as 47k. I believe that the GitHub values are more correct since they will produce an offset that sets the drain of Q3, the DMG2305UX PFET, 43mV below the source when the circuit is balanced (in equilibrium). The offset can be calculated from this equation:

Vos = kT/q ln(IR3/IR2) ~ kT/q ln((Vdd - VGS3)R2/((Vdd - Vbe)R3)) , where kT/q ~ 26mV @ room temp

The offset is a requirement since without it the circuit will attempt to keep the Vds across Q3 near zero which will force Q3's gate to be near ground any time there is current flowing into the output. That will cause long turn-off times for Q3 when the input voltage drops below the output. The circuit will behave more like a comparator if the two resistor values are equal.

The main concern of this circuit is how it is compensated to be stable under all conditions. Usually there is a dominate pole compensation capacitor - either the 47uF load capacitor or the Cgs of Q3 - that keeps the circuit from oscillating. I'm assuming that the designers have done their job well and it is stable.