At nanoscale silicon levels (as used in modern consumer VLSI chips), there are a significant number of effects that limit the lifespan of integrated circuits based on these technologies.
When manufactured, wafers are doped in a multi-step process that basically involves diffusing dopant atoms through the top few nanometres of silicon. Ion implantation is also used in some steps to precision-dope certain areas of silicon.
Oxide layers are also deposited. These typically form the gates of the FETs on the wafer substrate.
Conductive wires are also laid on top of the silicon matrix - the interconnect.
The interconnect can be degraded through electromigration.
The oxide layers can be degraded through electron tunnelling. Electrons end up trapped in the oxide layer causing a field bias that renders the transistor useless.
High temperatures and voltages can cause dopant to migrate.
All of these effects are intensely accelerated through higher temperature and higher voltages - which is why chips are tested at the absolute maximum of both in order to provide an ultimate worst-case MTTF. This MTTF is extrapolated down to nominal voltages and temperatures to give the "quoted lifespan" of the IC.
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