rowan.bradley
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Interfacing to IO pins via 8085 bus

Sun Nov 03, 2013 2:13 pm

I work on a system based on the 80320 (8051 family) microprocessor. I'm thinking of trying to replace the main processor with a modern processor that will have much more memory, USB ports, WiFi, Ethernet, Linux or other real time exec etc. There are a lot of special purpose IO boards that I really have to keep, so what I think I need is a modern processor with a good way of interfacing to these legacy IO boards. The IO is all memory mapped, so I think all I need is a way of reading and writing a byte at a time to/from locations with a 16-bit address. I could obviously do it just by using 16 GPIO pins set to Output for the address bus, plus 8 GPIO pins which are input for read and output for write, plus a couple more pins for ALE and Write Enable. I need to be able to read and write blocks of IO data quite quickly to/from these boards, because some of this stuff is quite time critical. Ideally they would be read and writeable as a block of main memory so I can use the new processor's instruction set to access them. So in this case the requirement is to adapt the 8051 bus to the new processor's bus within an address block. I wonder whether some kind of FPGA would do this well, but I have no idea what's available.

Has anyone done something like this? Any suggestions on how best to go about it, or things to avoid?

Thanks - Rowan

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FLYFISH TECHNOLOGIES
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Re: Interfacing to IO pins via 8085 bus

Sun Nov 03, 2013 3:37 pm

Hi Rowan,

There are several possible paths leading to proper solution...
You wrote something about quite time critical timings, but nothing about amount of data. However, my path according to your info would be to add a processor between 8085 bus and RasPi USB port. This additional processor would take care of 8085 bus timings with data pump from it on one side, and feed data via USB to RasPi for further processing.

I wrote about "processor" where this interface can actually be implemented with one of many breadboards/modules available on the market, containing microcontroller, USB, some power supply elements (if needed) etc.

Yes, I done something similar in the past, so if you have further questions, feel free to ask.

Best regards, Ivan Zilic.
Running out of GPIO pins and/or need to read analog values?
Solution: http://www.flyfish-tech.com/FF32

rowan.bradley
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Joined: Sun Nov 03, 2013 1:02 pm

Re: Interfacing to IO pins via 8085 bus

Sun Nov 03, 2013 6:20 pm

Thanks very much for your response. With respect to the number of IO pins required in the system, a typical system might have up to 640 pins. A large system, might have up to 2000 pins. These are arranged in 8-bit bytes on the 8-bit 8051 bus.
My thoughts are that using a second processor to adapt to the 8051 bus is more complicated than (I hope) it needs to be. We are really only talking about writing to and reading from a block of external memory. Using USB as the transfer medium would introduce a substantial protocol stack and require an awful lot of processor cycles to transfer 1 byte of information, which should really (and in the 8051 solution does) only take a single instruction.

The Rasp Pi doesn't seem to have any bus extender type interface, which I imagine might be ideal for this purpose. It's not possible to use the SD card, or the CSI or the DSI interface is it? Or JTAG?

By the way, it doesn't have to be a Rasp Pi - any processor on which I can run a C application and have some kind of OS, Ethernet, WiFi, USB, CF cards etc. would do.

Thanks - Rowan

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FLYFISH TECHNOLOGIES
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Re: Interfacing to IO pins via 8085 bus

Sun Nov 03, 2013 7:17 pm

Hi Rowan,
rowan.bradley wrote:We are really only talking about writing to and reading from a block of external memory.
Aha, I understood that timing is something a special attention should be paid for... ;-)

Next approximation: ;-)
1) if reading/writing addresses are sequential, then you can add a counter to compose 16-bit address,
2) if addresses are random, SPI to parallel chip could do the job (if data troughput can be handled due to decreased "bandwidth").

So, the overall needed pins count would be something like 8 (data bus) + 1 (read/write) + 1 ("chip select" or however your system calls it) + 2 (option 1: counter reset & clock or option 2: SPI) [ + 1optionally, if you need "output enable"].
These signals bit-banging should be straight-forward...

rowan.bradley wrote:By the way, it doesn't have to be a Rasp Pi
Sorry, wrong forum... :lol:
RasPi is nice... stay with it. ;-)


Best wishes, Ivan Zilic.
Running out of GPIO pins and/or need to read analog values?
Solution: http://www.flyfish-tech.com/FF32

rowan.bradley
Posts: 10
Joined: Sun Nov 03, 2013 1:02 pm

Re: Interfacing to IO pins via 8085 bus

Fri Dec 13, 2013 12:46 pm

Is there not some kind of address/databus which the processor uses to access external memory, and/or external peripheral registers (like old microprocessors used to have)? If so, then it seems to me far preferable to design an interface between this and the old 8051 bus than to do it all by bit banging GPIO pins. Maybe this interface could be in an FPGA. This could deal with the slower speed of the old bus. Ideally I should be able to read a byte from a peripheral address in a single assembly instruction.

Thanks - Rowan

notro
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Re: Interfacing to IO pins via 8085 bus

Fri Dec 13, 2013 4:43 pm

One solution for the Raspberry Pi, could be using SPI and the Guzunty, which uses a Xilinx XC9500XL CPLD: https://github.com/Guzunty/Pi/wiki
The vanilla SPI master driver (spi_bcm2708) is a bit limited when it comes to speed choices. You can only choose speeds with a powers of two divisor: 16, 32, 64, 125MHz (250MHz clock). 32MHz is the fastest reported working speed, 64MHz won't work. By lifting a limitation in the driver, you can at least do 48MHz: https://github.com/notro/spi-bcm2708/wi ... ck-divider. But of course, pushing the boundaries might not be the best in an industrial application.

For high speed you can have a look at the BeagleBone Black and it's Programmable Real-Time Unit and Industrial Communication Subsystem (PRU-ICSS): http://analogdigitallab.org/articles/be ... n-pru-icss

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