Reading the peripheral docs, I can't seem to figure out which bit of which IRQ pending register gets raised when a DMA interrupt is signaled. I realize that there is a register that is part of the DMA peripheral that contains a bit for each DMA controller that is raised when that controller's interrupt fires, but using that to determine whether or not ANY of the DMA controllers have signaled an interrupt seems to go against the correct way of handling interrupts, which is to use the IRQ pending registers to determine which "class" of interrupt has fired and then branch to a subroutine to handle that type (by checking that peripheral's registers to determine which interrupt needs to be handled).
Can anyone provide any insight here?
Thanks!