The chip I use for 3.3V RS-485 is the MAX3485 chip - half duplex, takes input from TTL level serial.
It has RE# and DE lines for switching to between receive and transmit - how you drive those is up to you. I have seen schematics with MOSFETs, and with 555 timers. Ideally you would drive it from a GPIO line and control it via software. Easy enough to switch to TX before transmitting - the trick though is to switch back to RS immediately the transmission has finished...
That's the bit I'm struggling with right now if anyone has any clues - how to delay until the last bit has left the UART. I'm guessing that step one is to switch the IO stream to un-buffered mode (simple enough), then do your transmitting. At that point the output data should all either be transmitted or in the UART's hardware buffer. So how can I probe that buffer to see if it's empty?
Is the Pi using the "Mini UART" for the console? If so there is the register AUX_MU_LSR_REG (0x7E21 5054) which has bit 6 "Transmitter idle" - "This bit is set if the transmit FIFO is empty and the
transmitter is idle. (Finished shifting out the last bit)."
If it's not using the mini uart, but using the main UART, then the register UART_FR looks interesting. It has the flag "TXFE " - "Transmit FIFO empty.". However, it is slyghtly complecated:
The meaning of this bit depends on the state of the FEN bit in the Line Control Register, UARTLCR_LCRH.
If the FIFO is disabled, this bit is set when the transmit holding register is empty.
If the FIFO is enabled, the TXFE bit is set when the transmit FIFO is empty. This bit does not indicate if there is data in the transmit shift register.
So you'd have to combine that with BUSY in the same register which indicates that the UART is actively transmitting data. Wait for the FIFO to empty, then wait for the UART to become idle.
So... My question is, given all that lot, what is the best way to delay my program after transmitting data through the UART to ensure that all the data has left the UART before continuing with my program?