tarkshya
Posts: 47
Joined: Tue Nov 03, 2015 7:28 pm

Clearing pending Core timer interrupts / Architected timers

Sat Jun 23, 2018 5:15 am

Hi,

In the document QA7_rev3.4.pdf,
section 4.6 states -

The registers allow you to enable or
disable an IRQ or FIQ interrupt. They cannot clear an pending interrupts. For that and other details of the
timers, read the Cortex-A7-coprocessor description.

In the Armv7 architecture reference manual (issue c.d) , section B8.1, page b8-1954 says this -

In the timer control register CNTP_CTL, CNTHP_CTL, or CNTV_CTL:
— The timer is enabled.
— The timer output signal is not masked.
This means that, to deassert the timer output signal, software must do one of the following:
• Reprogram the timer registers so that neither of the timer conditions is met.
• Mask the timer output signal, in the timer control register.
• Disable the timer, in the timer control register.



So if i program CNTP_CTL & CNTP_TVAL , and lets say i program one of the core 0 timer registers for interrupts, at address 0x4000_0000, i am able to get the interrupts, but i am not able to clear the pending interrupts. Does anyone know how to clear the interrupt pending status for this timer?

Isnt the architected timer supposed to be one-shot (with automatic clearing of the status bit) ?

Linux seems to be overwriting the mask bit (in timer handler function) and also resetting the cntp_tval in set_next_event() function - https://github.com/raspberrypi/linux/bl ... ch_timer.c

Not sure whether this is the right way to do it.


N.B - this is for bare-metal code (linux code is cited only for reference). This is running on a Raspberry pi 2 (cortex a7 version)


Could someone tell the exact way to clear the pending interrupt ?


Thanks

eggmansan
Posts: 2
Joined: Tue May 22, 2018 3:27 am

Re: Clearing pending Core timer interrupts / Architected timers

Sun Jun 24, 2018 4:05 am

hello

I checked generic timer function on QEMU. I not checked real hardware.

My handler code is below.
Generic timer interrupt clear when set cntv_tval to next value

Code: Select all

void c_irq_handler(void)
{
    if (read_core0timer_pending() & 0x08 ) {
        write_cntv_tval(cntfrq);    // clear cntv interrupt and set next 1sec timer.

        uart_puts("core0timer_pendig : ");
        uart_hex_puts(read_core0timer_pending());
        uart_puts("handler CNTV_TVAL : ");
        uart_hex_puts(read_cntv_tval());
        uart_puts("handler CNTVCT    : ");
        uart_hex_puts( (uint32_t) read_cntvct() & 0xFFFFFFFF);
    }
    return;
}
log :

Code: Select all

$ qemu-system-arm -M raspi2 -m 128 -serial mon:stdio -nographic -kernel kernel.elf
CNTFRQ  : 0x3B9ACA0
CNTV_TVAL: 0x3B99B62
core0timer_pendig : 0x0
handler CNTV_TVAL : 0x3B96C9C
handler CNTVCT    : 0x3D7E30F
my code is on github.

for QEMU -m raspi2
https://github.com/eggman/raspberrypi/t ... i2/timer01

for QEMU -m raspi3
https://github.com/eggman/raspberrypi/t ... i3/timer01

tarkshya
Posts: 47
Joined: Tue Nov 03, 2015 7:28 pm

Re: Clearing pending Core timer interrupts / Architected timers

Sun Jun 24, 2018 3:10 pm

@eggmansan

As mentioned in the original post, linux seems to be doing that (plus modifiying imask & istatus bits), i was curious if the other options as mentioned in the armv7 arm, would equally work (or probably my reading is wrong) or if there exists other means of clearing the pending interrupt. My previous experiments too showed what you have mentioned (setting the cntp_tval).

Thanks once again for the confirmation on qemu.

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