LdB
Posts: 782
Joined: Wed Dec 07, 2016 2:29 pm

AARCH64 MMU and ldaxr/stlrb semphore

Thu Jun 14, 2018 5:49 am

This is really for lizzard I finished getting the AARCH64 with MMU and ldaxr/stlrb semaphore up on all 4 cores

https://github.com/LdB-ECM/Raspberry-Pi ... tualmemory

Now I am going to have to do this otherwise I will get a snide comment.
I do not suggest this is how you do multicore code it is simply a test setup !!!!.
I would also thank bzt for his initial work and sample which I hacked the hell out of :-)
Okay that said my bootstub runs each core thru a setup process and then parks them back so I can command them to enter a standard C function. This functionality is a feature of my bootstub if you use your own bootstub you will need to engineer something. I use it for testing like this and kicking Virtual Machine code.

So on the test code, core 0 enters and creates the MMU table.
Table1 is a 2GB 1:1 Map of the memory from 0x0 to 0x40200000 which is the just over 1GB area of the Pi memory plus the hardware area described in QA7_rev3.4.pdf
Table2 is a virtual table and unused in this sample
The core then loads the tables and turns on it's MMU and all caching giving it the ability to run an aquire semaphore.

If the MMU fails the semaphore_inc code will deadlock as it will not be able to get a clean aquire.

Core0 then using an aquire semaphore, commands each other Core to load the same table they will release the semaphore when they complete so I know they have done it.

Finally then it does some testing to make sure each core can see a semaphore lock.

All I was trying to do was check the MMU code was correct and worked on all 4 cores. You will need to lookup and make more synchronizing primitives (ARM has a whitepaper on them). That however should get you started.

This is probably for lizzard but a BIG WARNING once you have the MMU engaged you will need MEMORY BARRIERS on hardware access. My serial code wouldn't even work properly without placing them on it.

A side question for people, does anyone know if we are allowed to turn the L2 cache on over the VC memory area. I haven't got memory barriers setup on my graphics code so wan't able to test?

StevoD
Posts: 19
Joined: Tue Aug 29, 2017 11:37 am

Re: AARCH64 MMU and ldaxr/stlrb semphore

Thu Jun 14, 2018 11:21 am

LdB wrote:
Thu Jun 14, 2018 5:49 am
A side question for people, does anyone know if we are allowed to turn the L2 cache on over the VC memory area. I haven't got memory barriers setup on my graphics code so wan't able to test?
ARM cpu has 4 x L1 cache and 1 x L2 cache which is shared by all 4 of them, VC has L2 cache which is separate from ARM cache. Do not confuse them.

LdB
Posts: 782
Joined: Wed Dec 07, 2016 2:29 pm

Re: AARCH64 MMU and ldaxr/stlrb semphore

Thu Jun 14, 2018 1:04 pm

StevoD wrote:
Thu Jun 14, 2018 11:21 am
ARM cpu has 4 x L1 cache and 1 x L2 cache which is shared by all 4 of them, VC has L2 cache which is separate from ARM cache. Do not confuse them.
What I am asking is can I turn the cache on in the MMU table over the area of the VC4 memory it owns so you can theoretically write/read faster to the framebuffer it gives you?

StevoD
Posts: 19
Joined: Tue Aug 29, 2017 11:37 am

Re: AARCH64 MMU and ldaxr/stlrb semphore

Thu Jun 14, 2018 1:08 pm

LdB wrote:
Thu Jun 14, 2018 1:04 pm
What I am asking is can I turn the cache on in the MMU table over the area of the VC4 memory it owns so you can theoretically write/read faster to the framebuffer it gives you?
Yes.

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