Hi,HiassofT wrote: ↑Tue Oct 24, 2017 7:53 amPhil's explanation is correct, here's how the I2S and clock signals wiring will look like:
FPGA is the clock master and provides the following clock outputs:
- a single BCLK output, this is connected to both RPI and codec BCLK inputs.
- a MCLK output to the codec
- a LRCLK_RPI output to the RPi
- a LRCLK_CODEC output to the codec
FPGA has 2 clock inputs from the 45/49MHz oscillators
FPGA has a bunch of control inputs for rate control, 45/49MHz selection and I2S clock enable/disable. These are connected to RPi GPIOs.
In addition to that we wire the I2S data signals directly from RPi to codec:
- RPi I2S data out is connected to codec I2S data in
- RPi I2S data in is connected to codec I2S data out