Burngate wrote:It seems to be getting more and more complicated - and the more there is, the more that can fail, leaving it in a non-safe condition.
Assuming you want it to fail safely within a second or so, how about this?
FailSafeOP.png
As long as the first fet is hit more than once a second, it'll hold the second one on. If not, the second fet will go off after another second.
Just off the top of my head, how about just the one FET, series capacitor to the gate and high value resistor from G to S, as you have, and switch the GPIO between output high and input tri-state?
The series C blocks DC if the GPIO sticks high.
Setting the pin to output high injects charge into the gate turning on the FET. The high value resistance discharges the gate in a second or so.
Output low turns FET off.
Stuck high FET turns off.
Keep pulsing out high/ input tri-state to keep the FET on.
Maybe add additional capacitance to the gate.