You seem to be confusing the page size in the memory management unit with the cache line size in the various levels of cache. There is absolutely no relation between the sizes, except that you can assume that each will be a power of two with natural alignment, so that a page always consists of a power of two number of cache lines.
The page size is used for memory access protection, swapping, and memory mapping of files. You can get it fairly portably at run time using sysconf(3): http://man7.org/linux/man-pages/man3/sysconf.3.html
The cache system is used to improve performance by reducing accesses to main memory. On some Linux platforms, you can get the line sizes using /sys, but this does not appear to be implemented on the Pi: http://stackoverflow.com/questions/7946 ... -line-size
On x86, the smallest page size is 4K, while the biggest cache line size is normally 64 bytes. I think that both ARMv6 and ARMv7 are 4K and 32 bytes.
Because of cache associativity, spreading data widely apart on page boundaries or at fractions of the total cache size may force them into addresses that must share the same subset of the cache slots.
I am not sure whether your concern about cores dirtying each others memory is valid or not. Perhaps you could try some benchmarks at various layouts. If you can observe a difference you will also find the best layout to minimize it at the same time. Preferably keep the sizes configurable so you can test again in the completed application.