I did the following set up and executed the test case listed below.
Both the RPis(PiA Master - PiB Slave) are connected over SPI(with common GND) as a test setup.
The issue is that, the FIFO flags in FR register doesn't set. I checked with all the 4 modes of CPHA and CPOL.
Step1 : Configured PiB as SPI slave and keep looping/waiting for data in RX FIFO using "RX FIFO Full" flag. I.e., read the data from DR only when the RX FIFO is full.
Step2 : Configured PiA as master and send some bytes of data.
In this case, the "RX FIFO full" flag doesn't set at all.
On the other hand, the SW checks if there is some data in RX FIFO using "RXFE RX FIFO Empty" flag, which is always SET(implies no data).
Please note, I am doing these changes from userspace after adding my enhancements to BCM2835 Library form http://www.airspayce.com/mikem/bcm2835/index.html
I would like to know if some one has already realized SPI slave in RPi either from userland or kernel level using BSC /SPI slave interface.
Any ideas to test the RPis communication over SPI are welcomed.