jamesh wrote: ↑Mon Nov 02, 2020 12:18 pm
lb wrote: ↑Mon Nov 02, 2020 11:44 am
It's called binning and it's hardly new. Every chip manufacturer does it!
Actually, it's more of a better clock gating in the C0 chip means we can power down more parts of the chip not ins use, which means less heat, which means more ability for higher clocks, which is boosted when combined with the high capacity heat spreader in the Pi 400.
Not sure we do binning.
but which peripherals are even unused enough to reduce the heat generation when gated?
is it just things like DSI/CSI being turned off, since the pi400 lacks those connectors?
or is it features the public doesn't even know of, that you cant name?
jamesh wrote: ↑Mon Nov 02, 2020 11:23 am
GaryH1 wrote: ↑Mon Nov 02, 2020 11:19 am
JamesH - what's the type code that is going to be used for this model (i.e. the one in the model's revision code)?
13, the docs have been updated.
ah, i had seen 13 in a start4.elf a few months ago, but i didnt know what it was, never expected something like this