RichardS wrote: ↑Thu Jun 07, 2018 1:50 am
I'm surprised. I thought that some of the Pi3B+ changes not related to WiFi, like the more powerful CPU, and POE (Power Over Ethernet) capability had already filtered down to the Pi2B, since logically this is the model that MOST needs faster Ethernet, and MOST needs POE, since it has no WiFi.
It's the same SoC, just flipped over and mirrored (keeping the contacts in the same places) with a heat spreader and using the PCB as a heat sink. The improved thermal handling permits a higher CPU clock. A "de-rated" (probably chips that a binned differently because they don't test at 1.2GHz) is used on the revised Pi2B, the v1.2 board. In theory, I'm reasonably sure that the RPT could use the B0 stepping as used on the Pi3B+ on the Pi2Bv1.2 board, though it would make more sense to redesign the board for the better thermal conditions and--as you note--the PoE circuitry. In "Off Topic" there is a thread discussing whether or not the Pi3A+ would be a good idea. You might start a similar thread making the case for a Pi2B+. Of course, PoE support would be pointless on a Pi3A+...
I suppose you could use a distributed network of Pi3B+ models as "access points" in an application using both powered Ethernet and WiFi, but I have always felt that the whole point of the Pi2B was to offer equivalent performance MINUS the WiFi, specifically for those corporate applications where wired networking is used in preference to WiFi because WiFi networking is not permissible due to security concerns - and given this situation, it would seem that it's actually the Pi2B model that would have most benefited from GigE and POE.
The Pi2Bv1.2 runs at the same 900MHz that the Pi2Bv1.1 did, even though it has the same SoC design that the Pi3B does. So it's not *just* a Pi3B without WiFi. It's also slower, and therefore has fewer thermal issues under load. That does mean, though, those chips that don't test as good at full speed can be used to make Pis thereby increasing the effective manufacturing yield and reducing per-chip cost through fewer that have to be thrown away.