SonicWave
Posts: 22
Joined: Mon Mar 19, 2018 1:10 pm

Configuring interrupts and adress of routine

Mon Mar 19, 2018 1:26 pm

I finally figured out how to run ARMv6 assembler on my Raspberry Pi B+, I started toggling some GPIOs:

Code: Select all

.section .init
 .global main
 main:
    /* Set GPIO Pin 2 as Output */
    ldr r0,=0x20200000
    mov r1,#1
    lsl r1,#6
    str r1,[r0]

infty:
    /* Set GPIO Pin 2 High */
    mov r1,#1
    lsl r1,#2
    str r1,[r0,#0x1C]

    /* Set GPIO Pin 2 Low */
    mov r1,#1
    lsl r1,#2
    str r1,[r0,#0x28]

    b   infty
    
I used these commands:
arm-none-eabi-as test.s
arm-none-eabi-objcopy a.out -O binary kernel.img
and replaced the kernel.img with the kernel.img from raspbian.

I have a few questions now:

1. I only measured about 6MHz of toggle speed even though I think there is not much code which could be dropped to speed things up, so how am I able to get the 21 MHz I read about on this forum?

2. I would like to drive a small 4-wire SPI display (128x128 Pixel) with the integraded Hardware-SPI as a first project. Is there enough documentation for it to work or should I rather stick to bit-banging?

LdB
Posts: 1209
Joined: Wed Dec 07, 2016 2:29 pm

Re: Configuring interrupts and adress of routine

Mon Mar 19, 2018 2:36 pm

I don't know about the screen will leave that for others to comment.
SonicWave wrote:
Mon Mar 19, 2018 1:26 pm
1. I only measured about 6MHz of toggle speed even though I think there is not much code which could be dropped to speed things up, so how am I able to get the 21 MHz I read about on this forum?
1. You haven't turned on any of the caches which is your responsibility in baremetal

Code: Select all

.equ SCTLR_ENABLE_DATA_CACHE,		0x4
.equ SCTLR_ENABLE_BRANCH_PREDICTION,	0x800
.equ SCTLR_ENABLE_INSTRUCTION_CACHE,	0x1000
    mrc p15,0,r0,c1,c0,0					;@ R0 = System Control Register

    /* Enable caches and branch prediction onto R0 register */
    orr r0, #SCTLR_ENABLE_BRANCH_PREDICTION
    orr r0, #SCTLR_ENABLE_DATA_CACHE
    orr r0, #SCTLR_ENABLE_INSTRUCTION_CACHE

    mcr p15,0,r0,c1,c0,0					;@ System Control Register = R0
2. Tighten your code it is the same value to set or clear that is why it's a different register.

Code: Select all

    mov r1,#1
    lsl r1,#2
infty:
    /* Set GPIO Pin 2 High */
    str r1,[r0,#0x1C]
    /* Set GPIO Pin 2 Low */
    str r1,[r0,#0x28]
    b   infty
See how you go with that

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