I typically max out the NAS with about 8.3 MB/s, so are 20 MB/s feasible with 3B+?

Still a shared USB/Gig ethernet controller. Mine is the fastest thing on my network (it's the only thing doing 5.4GHz WiFi). It runs the AIY VoiceHAT ("OK, Google") stuff really well.
as the blog says it is still on the end of the usb 2 bus so it is shared,
Of course not since it's still 'shared bus' here. In theory we could get something around 19 MB/s when USB disks and Gigabit Ethernet is used at the same time. But there's a serious concern called 'USB bus contention' that was not an issue with the old LAN9514 (Fast Ethernet) but could now become a problem with Gigabit Ethernet.pi-anazazi wrote: ↑Wed Mar 14, 2018 11:10 amWill the faster ethernet increase the throughput by factor 3?
The chip also provides the USB2 hub.
Nope. On these pins the 'power' provided by an Ethernet cable is fed to the PoE HAT where some circuitry sits to negotiate a PoE supply with the switch (see starting from 'Stages of powering up a PoE link'). Then stable 5V are generated and most probably fed to pins 4/6 on the GPIO header.KevinSwansea wrote: ↑Wed Mar 14, 2018 11:47 amCould the 4 PoE pins be used as a method to connect a barrel-type connector to the Pi
Don't think the current SoC can do beyond 1 GB — can it?
Not around here. We just use a $1 PoE splitter/injector. Like so:...an Ethernet cable is fed to the PoE HAT where some circuitry sits to negotiate a PoE supply with the switch...
That's a shame, it would be good to be able to provide direct 5V power to the Pi without either using the micro-USB port or tying up GPIO pins (for example, some external motor controllers provide a stable 5V out for external hardware, or some people might prefer the ability to have a power connector external to the board, rather than plugging and unplugging cables directly on the board itself).tkaiser wrote: ↑Wed Mar 14, 2018 12:28 pmNope. On these pins the 'power' provided by an Ethernet cable is fed to the PoE HAT where some circuitry sits to negotiate a PoE supply with the switch (see starting from 'Stages of powering up a PoE link'). Then stable 5V are generated and most probably fed to pins 4/6 on the GPIO header.KevinSwansea wrote: ↑Wed Mar 14, 2018 11:47 amCould the 4 PoE pins be used as a method to connect a barrel-type connector to the Pi
Welcome to Gigabit Ethernet then where passive PoE as you are used to doesn't work any more
The 7515 is a BGA package, not so easily hackable by us cf the QFN of the old LAN9515. If they have not routed those extra four balls out, then no chance for the 5th & 6th USB.fanoush wrote: ↑Wed Mar 14, 2018 12:37 pmThe http://www.microchip.com/wwwproducts/Pr ... 15/LAN9514 page says:
# Downstream Ethernet/USB Ports Ethenet x1, USB2.0 x6
Downstream USB Ports 6
but on the top it only says Ethernet Bridge with 4-port USB 2.0 Hub
So what are those 2 extra ports for? Could we possibly have two extra usb ports on some test points?
Well, doing this works since the 1st Pi, we simply feed whole fleets of RPi with 5.2V generated by a buck converter from 24V (using passive PoE). But when inserting 5V through pins 4/6 you avoid some protection circuitry so only do this with a clean and regulated power source. I would believe with the PoE HAT additional protection circuitry will sit there.KevinSwansea wrote: ↑Wed Mar 14, 2018 1:08 pmit would be good to be able to provide direct 5V power to the Pi without either using the micro-USB port or tying up GPIO pins
What part of "You're limited to 1GB with the VC4 videocore (the SoC on ALL raspberries)" are you failing to grasp? More than a gig of RAM needs a new videocore and development of that won't be cheap or quick. The 3B+ is a point release of hardware changes that can be done by re-engineering the existing silicon rather than developing a completely new system-on-a-chip.
Ethernet socket hasn't moved. Do you mean the chip? That's a new chip, so the chances of it moving are quite high....if you case replies on the particular position of chips on the board then you are out of luck. And there is NO WAY that we are going to design boards to continue to fit every case on the market. We'd never be able to add ANY new features.runboy93 wrote: ↑Wed Mar 14, 2018 10:31 amEthernet moved, reason why fanless case from my signature isn't supported. Leaves empty spot.DougieLawson wrote: ↑Wed Mar 14, 2018 10:00 amThe board layout is identical to the 3B apart from the four extra POE pins.
For example, this is supported ofc, all is needed is right dimensions, nothing else:
http://www.akasa.com.tw/update.php?tpl= ... A-RA03-A1B
I am not having problems grasping anything, thank youDougieLawson wrote: ↑Wed Mar 14, 2018 1:26 pmWhat part of "You're limited to 1GB with the VC4 videocore (the SoC on ALL raspberries)" are you failing to grasp? More than a gig of RAM needs a new videocore and development of that won't be cheap or quick. The 3B+ is a point release of hardware changes that can be done by re-engineering the existing silicon rather than developing a completely new system-on-a-chip.
You're going to have to wait for "Raspberry Pi version next" when that happens.