CM4 launched

[ejolson]

Would it be possible to use an NVMe SSD and skip USB3 completely?

Did you watch the video in the launch blog post? That was one of the uses of the PCIe slot that was discussed.

Is there a video? Woohoo! Time to cook some popcorn. Thanks for the pointer; I hadn't noticed.

Is there a common USB3 peripheral other than external storage?

[timg236]

Does the bootloader support USB boot from a xHCI card? Basically does it recognise other xHCI host controllers.

Yes, although, obviously you need to verify compatibility with the external xHCI controller whilst designing your CM4 product.

[W. H. Heydt]

Would it be possible to use an NVMe SSD and skip USB3 completely?

Did you watch the video in the launch blog post? That was one of the uses of the PCIe slot that was discussed.

Is there a video? Woohoo! Time to cook some popcorn. Thanks for the pointer; I hadn't noticed.

Is there a common USB3 peripheral other than external storage?

See the video already referenced.

[geerlingguy]

I'm trying to get a GeForce GT 710 working, but have run into my first major speed bump, having no available BAR space for the GPU to allocate. In a Twitter thread (https://twitter.com/domipheus/status/11 ... wsrc%5Etfw), it was mentioned that one may be able to adjust the allocation in the device tree, but in my searching (admittedly getting late at night) all I could find was the brcm,stb-pcie device, but am unsure of the next steps in trying to make it so the GPU can get all the address memory it needs.

Any ideas from someone who's a bit more familiar with PCIe? I also have an Intel 4 port 4xGbps network adapter on the way that I want to test with... I'm fearing I might run into a similar problem!

Why weren't those Broadcom engineers thinking about dropping more robust PCIe support into this little chip?

Edit: forgot to add, here's a gist where I've been doing some testing and jotting down my notes so far: https://gist.github.com/geerlingguy/9f1 ... 20308db2af

[plugwash]

IIRC graphics controllers are pretty unusual in taking up huge chunks of address space to address the huge amounts of on-card memory they have.

[geerlingguy]

IIRC graphics controllers are pretty unusual in taking up huge chunks of address space to address the huge amounts of on-card memory they have.

Yeah, in this case it looks like it's having trouble allocating more than 32MB:

Code: Select all

BAR 9 size 0x0c000000 ≈ 200 MB (fails)
BAR 1 size 0x08000000 ≈ 128 MB (fails)
BAR 3 size 0x02000000 ≈ 32 MB (fails)
BAR 5 size 0x0080 ≈ 128 bytes (fails with `no space for [io  size 0x0080]`)
BAR 8 ≈ 25 MB (succeeds)
BAR 0 ≈ 16 MB (succeeds)
BAR 6 ≈ 512 KB (succeeds)

I intentionally went with an older but seemingly reliable and popular GPU to try to see if it would work better than some monstrosity (and it cost a lot less too ha!).

[bensimmo]

Could try the 5.9 kernel that's in testing since that's probably the most up to date, the Nvidia's Nvidia drivers are not there yet though. (see 5.9 kernel topic, but I would spin out any talk on this away from cm4 and kernel talk.
maybe CM4 PCIE topic on its own.

[jdb]

IIRC graphics controllers are pretty unusual in taking up huge chunks of address space to address the huge amounts of on-card memory they have.

Yeah, in this case it looks like it's having trouble allocating more than 32MB:

Code: Select all

BAR 9 size 0x0c000000 ≈ 200 MB (fails)
BAR 1 size 0x08000000 ≈ 128 MB (fails)
BAR 3 size 0x02000000 ≈ 32 MB (fails)
BAR 5 size 0x0080 ≈ 128 bytes (fails with `no space for [io  size 0x0080]`)
BAR 8 ≈ 25 MB (succeeds)
BAR 0 ≈ 16 MB (succeeds)
BAR 6 ≈ 512 KB (succeeds)

I intentionally went with an older but seemingly reliable and popular GPU to try to see if it would work better than some monstrosity (and it cost a lot less too ha!).

The allocation for outbound *size* is probably fixable, as it's specified in the dt: https://github.com/raspberrypi/linux/bl ... .dtsi#L359


What's BAR5 requesting? Can you post sudo lspci -vvv output for the card? If it's legacy IO space then I doubt the RC supports that type of traffic.

[PhilE]

geerlingguy has started another thread about this (always fun for all concerned) here: viewtopic.php?f=133&t=288902

Please keep all discussion of PCIe windows to that thread.

[trejan]

geerlingguy has started another thread about this (always fun for all concerned) here: viewtopic.php?f=133&t=288902

Please keep all discussion of PCIe windows to that thread.

"You are not authorised to read this forum."

[gsh]

viewtopic.php?f=98&t=288902

[aBUGSworstnightmare]

envy
who's that 'geerlingguy' and why does he has access to CM4 + CM4IO already

[jamesh]

We send out review and beta test equipment to quite a lot of people under NDA.

[bifurkas]

There is an unfortunate location of the connectors. The connectors have no centering holes on the PCB, so It is impossible to keep the exact distance between this. In addition, a processor is located between the connectors, thermal deformation will be present. As a result, all this will lead to loss of contact in the connectors. IMHO

[fruitoftheloom]

envy
who's that 'geerlingguy' and why does he has access to CM4 + CM4IO already

https://www.jeffgeerling.com/

[cleverca22]

and also things like https://www.youtube.com/watch?v=YYDmaKP2m5M

[W. H. Heydt]

There is an unfortunate location of the connectors. The connectors have no centering holes on the PCB, so It is impossible to keep the exact distance between this. In addition, a processor is located between the connectors, thermal deformation will be present. As a result, all this will lead to loss of contact in the connectors. IMHO

Don't you think the RPT folks tested for problems like that?

[ejolson]

There is an unfortunate location of the connectors. The connectors have no centering holes on the PCB, so It is impossible to keep the exact distance between this. In addition, a processor is located between the connectors, thermal deformation will be present. As a result, all this will lead to loss of contact in the connectors. IMHO

Using two high-density connectors spaced far apart on a single rigid PCB is an unusual design for me to see as well. The CM4 itself has four mounting holes. Do you think those could be used to attach the module to a carrier board securely enough to avoid loss of contact over time from thermal contraction and expansion?

[trejan]

Using two high-density connectors spaced far apart on a single rigid PCB is an unusual design for me to see as well.

Dual connectors like on the CM4 is quite common on other system-on-modules. They're nearly always spaced apart with one connector on each end.

[ejolson]

There is an unfortunate location of the connectors. The connectors have no centering holes on the PCB, so It is impossible to keep the exact distance between this. In addition, a processor is located between the connectors, thermal deformation will be present. As a result, all this will lead to loss of contact in the connectors. IMHO

Don't you think the RPT folks tested for problems like that?

The custom built carrier boards that will be used in the field haven't been constructed yet. Only time will tell how many third-party projects have problems with this. My hope is that sufficient tolerances are built into the connectors themselves so reliability is not a continual problem.

It is worth noting the Jetson series all use single connectors but that an SO-DIMM connector similar to the Nano was rejected by the Pi engineers.

[bifurkas]

Don't you think the RPT folks tested for problems like that?

I am a practitioner. I do not use IO board, I make PCB and assemble boards myself. I do not know the capabilities of a RPT, but It will be difficult for me to properly solder the connectors

[ejolson]

Using two high-density connectors spaced far apart on a single rigid PCB is an unusual design for me to see as well.

Dual connectors like on the CM4 is quite common on other system-on-modules. They're nearly always spaced apart with one connector on each end.

That's reassuring. Have you seen the same kind of high density connector in such situations?

[bifurkas]

If the developers agree, then I would test the board in my design. Where to get? Not on sale.

[trejan]

That's reassuring. Have you seen the same kind of high density connector in such situations?

Yes. I've never had any problems with this type of connection. See the SoMs at https://www.intel.com/content/www/us/en ... dules.html for examples. Most of them have dual high density connectors on the bottom and the power hungry FPGA or SoC in the middle.

My experience is with boards which have gone through automated pick & place though. It'll be quite tricky to manually solder. The CM4 will work with only the "low" speed connector that has power + GPIOs + SD + Ethernet which makes it easier but you lose PCIe, USB, HDMI, CSI and DSI so not suitable for everything.

[trejan]

If the developers agree, then I would test the board in my design. Where to get? Not on sale.

viewtopic.php?f=98&t=288842&p=1746685&#p1746685 gives some details about availability and the long lead times on RS.