oweno
Posts: 27
Joined: Sat Feb 16, 2013 3:40 pm

I2C Problems on SDA

Thu Sep 20, 2018 4:38 pm

Asking this question here, still not certain if this is a CM / RPI issue or not. I thought it might be a problem with the I2C device itself (in this case an audio codec). But I've observed the behavior on 2 different slave device: the TLV320AIC23B and the compatible WM8731.

I'm debugging a single I2C master (Raspberry Pi Compute Module) connected to a single slave (a TLV320AIC23B or WM8731 audio codec on separate board)

They are connected by 3" jumper wires (4 wires SDA, SCL, PWR, GND). There are 4k7 pull up resistors on the master side.

About 20% of the time the slave doesn't successfully pull the line low for ACK and I can observe the following pulse in the scope, as if the slave is trying to ACK, but then fails:
SDS00001.png
SDS00001.png (51.38 KiB) Viewed 1109 times

And up close:
SDS00002.png
SDS00002.png (19.39 KiB) Viewed 1109 times

When I add 220 Ohm series resistors to SCL and SDA at the slave side, the problem goes away completely, but trying to understand why.

Is it possible SDA is anything other than open-drain and could be yanking the line high? raspi-gpio doesn't indicate anything strange about the pins:

Code: Select all

BANK0 (GPIO 0 to 27):
GPIO 0: level=1 fsel=0 func=INPUT
GPIO 1: level=1 fsel=0 func=INPUT
GPIO 2: level=1 fsel=4 alt=0 func=SDA1
GPIO 3: level=1 fsel=4 alt=0 func=SCL1
GPIO 4: level=1 fsel=0 func=INPUT
GPIO 5: level=1 fsel=0 func=INPUT
GPIO 6: level=1 fsel=0 func=INPUT
GPIO 7: level=1 fsel=0 func=INPUT
GPIO 8: level=1 fsel=0 func=INPUT
GPIO 9: level=0 fsel=0 func=INPUT
GPIO 10: level=0 fsel=0 func=INPUT
GPIO 11: level=0 fsel=0 func=INPUT
GPIO 12: level=0 fsel=0 func=INPUT
GPIO 13: level=0 fsel=0 func=INPUT
GPIO 14: level=0 fsel=0 func=INPUT
GPIO 15: level=0 fsel=0 func=INPUT
GPIO 16: level=0 fsel=0 func=INPUT
GPIO 17: level=0 fsel=0 func=INPUT
GPIO 18: level=1 fsel=4 alt=0 func=PCM_CLK
GPIO 19: level=0 fsel=4 alt=0 func=PCM_FS
GPIO 20: level=0 fsel=4 alt=0 func=PCM_DIN
GPIO 21: level=0 fsel=4 alt=0 func=PCM_DOUT
GPIO 22: level=0 fsel=0 func=INPUT
GPIO 23: level=0 fsel=0 func=INPUT
GPIO 24: level=0 fsel=0 func=INPUT
GPIO 25: level=0 fsel=0 func=INPUT
GPIO 26: level=0 fsel=0 func=INPUT
GPIO 27: level=0 fsel=0 func=INPUT
BANK1 (GPIO 28 to 45):
GPIO 28: level=0 fsel=0 func=INPUT
GPIO 29: level=0 fsel=0 func=INPUT
GPIO 30: level=0 fsel=0 func=INPUT
GPIO 31: level=0 fsel=0 func=INPUT
GPIO 32: level=0 fsel=0 func=INPUT
GPIO 33: level=0 fsel=0 func=INPUT
GPIO 34: level=1 fsel=0 func=INPUT
GPIO 35: level=1 fsel=0 func=INPUT
GPIO 36: level=1 fsel=0 func=INPUT
GPIO 37: level=0 fsel=0 func=INPUT
GPIO 38: level=0 fsel=0 func=INPUT
GPIO 39: level=0 fsel=0 func=INPUT
GPIO 40: level=0 fsel=0 func=INPUT
GPIO 41: level=0 fsel=0 func=INPUT
GPIO 42: level=0 fsel=0 func=INPUT
GPIO 43: level=0 fsel=0 func=INPUT
GPIO 44: level=0 fsel=0 func=INPUT
GPIO 45: level=0 fsel=0 func=INPUT
BANK2 (GPIO 46 to 53):
GPIO 46: level=1 fsel=0 func=INPUT
GPIO 47: level=1 fsel=1 func=OUTPUT
GPIO 48: level=0 fsel=4 alt=0 func=SD0_CLK
GPIO 49: level=1 fsel=4 alt=0 func=SD0_CMD
GPIO 50: level=1 fsel=4 alt=0 func=SD0_DAT0
GPIO 51: level=1 fsel=4 alt=0 func=SD0_DAT1
GPIO 52: level=1 fsel=4 alt=0 func=SD0_DAT2
GPIO 53: level=1 fsel=4 alt=0 func=SD0_DAT3

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joan
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Location: UK

Re: I2C Problems on SDA

Thu Sep 20, 2018 5:44 pm

I do not understand what you mean by "When I add 220 Ohm series resistors to SCL and SDA at the slave side". I guess one side is connected to SDA/SCL. What is the other end connected to?

oweno
Posts: 27
Joined: Sat Feb 16, 2013 3:40 pm

Re: I2C Problems on SDA

Thu Sep 20, 2018 6:29 pm

series resistors, Rs in this pic.

Rp = 4k7
Rs = 220 Ohm
Attachments
Untitled.png
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John Westlake
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Re: I2C Problems on SDA

Fri Sep 21, 2018 12:10 am

I'm not saying this is the case here - But I've seen IC's that use Active drive (Active pull-up) 'Open Drain' outputs for a very brief period to allow a faster edge (due to the Low impedance drive) - after this brief edge 'period' the outputs resort to standard Open Drain operation - we got caught out by this on a design using the TAS1020B....

You could test this yourself by removing the I2S pull-up resistors and see if you observe transition "Spikes" on the positive going edges indicating a brief active pull-up period...

oweno
Posts: 27
Joined: Sat Feb 16, 2013 3:40 pm

Re: I2C Problems on SDA

Fri Sep 21, 2018 2:53 pm

Thanks for this info. Removing pull-ups I can still see some activity on SDA and SCL, but not really spikes. I thought I read that GPIO 2 and 3 have weak internal (50k?) pull-ups, and what I see is in line with that, very slow rise times that do not make thresholds.

So I don't know if it is an active driver situation...

Just to rule out GPIO 2 and 3 contributing to the problem, I moved i2c1 to GPIO 44 and 45, but I get the same behavior as original post.

Brandon92
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Location: Netherlands

Re: I2C Problems on SDA

Fri Sep 21, 2018 3:52 pm

How did you wire everything to up. And what for wires are you using. Maybe a picture of your test setup?

Did you try a lower value resistor for the pull up (1,8k)? And is your clock speed within the specifications of the IC that you are using?

John Westlake
Posts: 84
Joined: Thu Nov 09, 2017 4:34 am

Re: I2C Problems on SDA

Fri Sep 21, 2018 3:57 pm

oweno wrote:
Fri Sep 21, 2018 2:53 pm
Thanks for this info. Removing pull-ups I can still see some activity on SDA and SCL, but not really spikes. I thought I read that GPIO 2 and 3 have weak internal (50k?) pull-ups, and what I see is in line with that, very slow rise times that do not make thresholds.

So I don't know if it is an active driver situation...

Just to rule out GPIO 2 and 3 contributing to the problem, I moved i2c1 to GPIO 44 and 45, but I get the same behavior as original post.
Good news is that your results rule out any issue with Active drive pull-up (there appears to be no 'Edge period' active pull-up)... but does not help solve your issue :(
Last edited by John Westlake on Fri Sep 21, 2018 4:03 pm, edited 1 time in total.

John Westlake
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Re: I2C Problems on SDA

Fri Sep 21, 2018 4:02 pm

Also, notice the Ground floor modulation one clock period proceeding and reasserts slightly post the successful ACK - I wounder if this is telling us anything? It really does look like some kind of pull-up is being released one clock period prior to the successful ACK.

oweno
Posts: 27
Joined: Sat Feb 16, 2013 3:40 pm

Re: I2C Problems on SDA

Fri Sep 21, 2018 6:02 pm

John Westlake wrote: It really does look like some kind of pull-up is being released one clock period prior to the successful ACK.
When I reduce pull-up resistor on SDA to 700 Ohm and use a 200 Ohm series resistor like this:

Image

I am able to take the following picture during a successful ACK:

Image

During the ACK it pulls all the way down for about 1/4 of the time, then lifts back up again. Is this what you were referring to?
Last edited by oweno on Fri Sep 21, 2018 6:22 pm, edited 3 times in total.

Brandon92
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Joined: Wed Jul 25, 2018 9:29 pm
Location: Netherlands

Re: I2C Problems on SDA

Fri Sep 21, 2018 6:05 pm

Can you do also the same test. Without the 200 ohm resistor.

oweno
Posts: 27
Joined: Sat Feb 16, 2013 3:40 pm

Re: I2C Problems on SDA

Fri Sep 21, 2018 6:07 pm

Sure, that looks like this. (see next post, sorry having trouble with these images!)
Last edited by oweno on Fri Sep 21, 2018 6:10 pm, edited 2 times in total.

oweno
Posts: 27
Joined: Sat Feb 16, 2013 3:40 pm

Re: I2C Problems on SDA

Fri Sep 21, 2018 6:09 pm

Without 220 Ohm resistor.
Attachments
SDS00005.png
SDS00005.png (22.93 KiB) Viewed 966 times

oweno
Posts: 27
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Re: I2C Problems on SDA

Fri Sep 21, 2018 6:16 pm

Brandon92 wrote:Maybe a picture of your test setup?
Here are 2 photos of test setup, with and without probes attached. The bottom board has the WM8731 audio codec. It also has socket for Compute Module, but wanted to take that out of the equation, so driving the board with the standard CMIO board.
Attachments
IMG_5332.jpg
IMG_5332.jpg (240.98 KiB) Viewed 959 times
IMG_5331.jpg
IMG_5331.jpg (231.73 KiB) Viewed 959 times

Brandon92
Posts: 532
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Location: Netherlands

Re: I2C Problems on SDA

Fri Sep 21, 2018 6:27 pm

Okay, if I see the last image that you sent. I thing the problem is with the CM3 module.
This is because when you send the data to the other IC. The voltage level doesn't go down to 0V. Unlike your clock. And the ack that is provided by the IC can pull the bus correctly low.

And are your wires not damaged, or are you using a breadboard?

edit
I see that dat you are using a other pcb for this test. Does that thin wire deliver enough power to the circuit. Because, I measured a couple weeks back the resistance of that wire. And it was more than I though.

aBUGSworstnightmare
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Re: I2C Problems on SDA

Sat Sep 22, 2018 7:38 am

Do you have another I2C device available, i.e an EEPROM? maybe you should crosscheck with another device if your I2C is working at all.
Why do you add fhese series resistors? You also might be better off with pull-ups in the range of 1k8 to 2k7 Ohms (rather than 4k7).

John Westlake
Posts: 84
Joined: Thu Nov 09, 2017 4:34 am

Re: I2C Problems on SDA

Sat Sep 22, 2018 1:56 pm

Reading the Wolfson Datasheet and the 2 Wire interface is described as a 2-wire MPU serial interface with NO mention of I2C so I would suspect I2C 'like' but not necessarily 100% I2C compatible....

"The WM8731/L supports a 2-wire MPU serial interface. "

Might be a clue here in this control register - worth trying...

"Note:
1. Pull Up/Down only present when Control Register Interface ACTIVE=0 to conserve power. "

From the top of Page 54 of the Wolfson Datasheet:-

0001001 Bit 0 Active Control

Activate Interface

1 = Active
0 = Inactive

Maybe you have set this bit High = Active interface? Try changing this Bit and see the effect on the 2 Wire interface....

oweno
Posts: 27
Joined: Sat Feb 16, 2013 3:40 pm

Re: I2C Problems on SDA

Sat Sep 22, 2018 2:49 pm

aBUGSworstnightmare wrote: Do you have another I2C device available, i.e an EEPROM?
Good point, should try another I2C device, although I have tried multiple boards / parts, so I'm pretty sure it is not a problem with specific part or CM. Also I get same result from both WM8731 and TLV320AIC23B, pin compatible devices from different manufacturers.
aBUGSworstnightmare wrote:Why do you add fhese series resistors?
This is really the question, why are the resistors necessary? I was reading series resistors like this can be used to filter noise picked up on I2C lines which is why I tried them. And while they do make it work, in this simple setup they should not be necessary. I haven't been able to capture any noise or spikes, so makes me think something else going on.
aBUGSworstnightmare wrote: You also might be better off with pull-ups in the range of 1k8 to 2k7 Ohms (rather than 4k7).
The situation does improve with lower value pull-ups, but doesn't go away...

oweno
Posts: 27
Joined: Sat Feb 16, 2013 3:40 pm

Re: I2C Problems on SDA

Sat Sep 22, 2018 2:57 pm

John Westlake wrote: Reading the Wolfson Datasheet and the 2 Wire interface is described as a 2-wire MPU serial interface with NO mention of I2C so I would suspect I2C 'like' but not necessarily 100% I2C compatible
I was wondering about this. But it might also be a licensing thing.
John Westlake wrote: Might be a clue here in this control register - worth trying...
Might be worth a shot, but they don't have that note listed next to the control interface SDIN, SCLK (I2C) pins. I already have MODE and CSB externally pulled low.

Thanks for everyone for looking into this btw!

John Westlake
Posts: 84
Joined: Thu Nov 09, 2017 4:34 am

Re: I2C Problems on SDA

Sat Sep 22, 2018 3:11 pm

oweno wrote:
Sat Sep 22, 2018 2:57 pm
John Westlake wrote: Reading the Wolfson Datasheet and the 2 Wire interface is described as a 2-wire MPU serial interface with NO mention of I2C so I would suspect I2C 'like' but not necessarily 100% I2C compatible
I was wondering about this. But it might also be a licensing thing.
Yes, I suspect it might be, everyone in the industry hates Cirrus Logic who are well known for being Patent sharks - so the industry returns the favor when ever possible....

I'm embarrassed to say that Cirrus Logic now Co. owns one of my Patents when they bought out Wolfson... :(
Last edited by John Westlake on Sat Sep 22, 2018 3:24 pm, edited 1 time in total.

John Westlake
Posts: 84
Joined: Thu Nov 09, 2017 4:34 am

Re: I2C Problems on SDA

Sat Sep 22, 2018 3:23 pm

oweno wrote:
Sat Sep 22, 2018 2:57 pm

Might be worth a shot, but they don't have that note listed next to the control interface SDIN, SCLK (I2C) pins. I already have MODE and CSB externally pulled low.
My bad, re-reading the Datasheet and the Pull-up refers to the mode select Pins themselves not the actual SDA/SCL pins....! Shame, it would have explained a lot...

John Westlake
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Joined: Thu Nov 09, 2017 4:34 am

Re: I2C Problems on SDA

Sat Sep 22, 2018 3:59 pm

Ok, maybe we have been looking at this all wrong, looking at your PCB design and I cannot see from the Low Res Picture any High Frequency PSU decoupling near the Digital PSU pin DBVDD - you could try placing a 100nF High Quality (= Low Inductance) Ceramic capacitor DIRECTLY across Pin 1 DBVDD and Pin 28 DGND (so across the top of the package with shortest leads (Maybe a SMD cap with a shortwire end attached to one side to stretch over the device).

The Package pinning on the 28Pin device is very poor with the DGND and VDD power pins furthest away from the center of the die - this will make the device more sensitive to PSU decoupling.... Also a real lack of Ground pins!!! Very poor IC design... knowledgeable designs will have the power (Ground pins) located towards the center of the package so pins 7/8 and 21/22...

QFN package is better - and maybe the QFN exposed Center pad will be connected to the substrate giving the lowest Ground inductance...

Also might be worth to double confirm DBVDD is connected to 3.3V and not that this power connection is missing and instead the devices I/O Pad ring is being powered via the internal ESD protect diodes / External pull-up resistors (You would not be the first to miss-off a power connection to a low power CMOS device and yet still see some 'Basic' function) :)

oweno
Posts: 27
Joined: Sat Feb 16, 2013 3:40 pm

Re: I2C Problems on SDA

Sat Sep 22, 2018 6:12 pm

John Westlake wrote: Cirrus Logic now Co. owns one of my Patents when they bought out Wolfson...
Interesting about Cirrus Logic, what was your patent for?

I double checked all the power pins were connected early on, wishing it was something like that.

But I'm glad you mentioned about PSU decoupling. There is a 100nF cap between DBVDD and GND, but the location is really not right. It is C55 in the attached close up.

You can also see a jumper wire connecting DVDD (27) to AVDD (8). Another thing the datasheet says is 'DVDD must be less than or equal to AVDD'. DVDD is 3.3V and I was running AVDD from separate 3.3V regulator... so should be fine, but got paranoid, what exactly do they mean 'equal'. so removed the AVDD regulator and jumped them together to be sure, but didn't change anything.

I am traveling for 2 days, but excited to try better decoupling cap when I'm back in at the office.
Attachments
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John Westlake
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Re: I2C Problems on SDA

Sat Sep 22, 2018 7:59 pm

oweno wrote:
Sat Sep 22, 2018 6:12 pm
John Westlake wrote: Cirrus Logic now Co. owns one of my Patents when they bought out Wolfson...
Interesting about Cirrus Logic, what was your patent for?
Gosh, IIRC it was a method to limit the Modulation index of a Class D Feedback system.... Keeping the Modulator well behaved during extremes of modulation... it was over 15 years ago , much development has passed though this designers mind since...

Layout is not great for C55, a longer then ideal current return loop between Ground and the Power Pin decoupling.... but I've worked in Asia for much of my working career and seen far far worst... Could it be you fitted in error say 100pF in C55 position instead of 100n or what have you?... but that would be wishful thinking...

Still, I'd try directly decoupling across the IC (Pin 1 to Pin 28) for the shortest current return path just to rule it out - and maybe save you pulling out any more hair...

Looking at your picture it does make me wonder where your HF decoupling is for the Digital Core voltage? Really you would want a 100nF slapped directly across pins 27 to pin 28....

If we are lucky :) added a couple of 100nF directly across Pin 1 - Pin 28 and Pin 27 - Pin 28 will resolve the problem :)... fingers crossed :)

The IC land pattern for the Chip Die mounted in the QFN package allows for a far better decoupling and Master clock routing... it looks like the 28 pin SSOP package is compromised... TBH, mounting QFN's packages is easier for a semi-retired old timer like me then fine pitch 28Pin SSOP anyway....

WRT voltage differences between Analogue and Digital rails - anything less the one diode junction voltage is Ok, if you have separated supply's (which you would want with Digital / Analogue domains) - then a pair of cross connected Schottky diodes across the two rails will insure correct conditions are always met during power cycling / operation etc.

Brandon92
Posts: 532
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Location: Netherlands

Re: I2C Problems on SDA

Sun Sep 23, 2018 1:51 pm

I think we need to see first the output signals of the module it self. So, without any device connected to the data bus. Than we can see why the voltage is not 0V. And this is well good by the clk.

I, also saw it the datasheet that it is a I2S data bus for the WM8731. And that is not the same as a I2C bus. So, praheps the communication between the two devices are wrong and want to "talk" at the same time to the data bus. And this could conclude why you see <0.6V at your databus when its "low". Because the Rpi thinks it is a x bit data bus. But, the the WM8731 has a audio data input between the 16-32bit.

oweno
Posts: 27
Joined: Sat Feb 16, 2013 3:40 pm

Re: I2C Problems on SDA

Sun Sep 23, 2018 2:42 pm

Brandon92 wrote: Than we can see why the voltage is not 0V. And this is well good by the clk.
The picture where data line (SDA) doesn't go to 0V is the result of using a small value pull-up, and is normal. I was only trying to illustrate what the signal looked like during the ACK phase. clock line (SCL) still has the larger (4k7) pull-up resistor which is why it looks different.
Brandon92 wrote: I, also saw it the datasheet that it is a I2S data bus for the WM8731. And that is not the same as a I2C bus
Yes, I2S is used for audio data, but this is not the issue. I2C is used to configure the device and is called '2 wire MPU control interface' or something in the data sheet. This might point to a compatibility problem, but most likely they can't use the I2C name in the datasheet because it is trademarked. This is a common situation with I2C.

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