Input protection with resistors

[markom8]

I've come across this method for protecting inputs with resistors (full article here https://www.digikey.com/en/articles/tec ... lectronics. Description says that this setup is actually simple voltage divider, but I'm unable to grasp how exactly this corelate to basic voltage divider diagram, which resistor is R1 and which is R2


Basic voltage divider diagram I'm talking about


If I understand correctly, R1 would be 100K resistor, connected as pull-up to 5V, and R2 would be 1K that goes to the switch?

I'm asking all this in order to learn, but also as option to protect my input GPIOs with DHT11 and DS18B20 on them. There are 4.7K pull-up resistors to 3.3V, what size serial resistor should I add in order make it work? Would this even work in my scenario?

[pcmanbob]

If you were to connect the circuit as shown you would kill your pi.

Do not use pull ups to 5v on a pi gpio they are not 5v tolerant.

in the link site they are talking about 5v microcontrollers not raspberry pi's.

my input GPIOs with DHT11 and DS18B20 on them. There are 4.7K pull-up resistors to 3.3V

that is the correct pull up for a pi gpio , you should not need anything else.

[neilgl]

+1 and I have about 6 metres of "long wire" with a 4K7 resistor pull-up for my DS18B20 to the pi.

[markom8]

If you were to connect the circuit as shown you would kill your pi.

Do not use pull ups to 5v on a pi gpio they are not 5v tolerant.

in the link site they are talking about 5v microcontrollers not raspberry pi's.

Yes, schematics is not Raspberry Pi specific, but I was thinking about RPi scenario with 3.3V pull-up.

[pcmanbob]

If you were to connect the circuit as shown you would kill your pi.

Do not use pull ups to 5v on a pi gpio they are not 5v tolerant.

in the link site they are talking about 5v microcontrollers not raspberry pi's.

Yes, schematics is not Raspberry Pi specific, but I was thinking about RPi scenario with 3.3V pull-up.

You already have a 4.7K pull up to 3.3v so what will adding another achieve ?

[markom8]

I'm hoping protection from ESD, induced EMI, switch closure, as stated in article. Although I'm not exactly sure what qualifies as "long wire" and are my 6m of utp cable long wire. And is using twisted cable enough protection?

[neilgl]

I am not using any twisted cable, just three wires. So far, no problems even though the wires are near a 240V water pump that switches on and off.

[boyoh]

You are given the option of setting the GPIO I/P
To a impedance level that the processor can
Respond to. In its high impedance state floating
It will not sink or source a working level signal
This being a logic level 0 low or 1 high, So you
MUST set it to a working impedance level by
Setting the internal resistance 50k or using a
External resister of 10k . If you want it to respond
To a logic 1 high you connect it to the 0v rail
If you want it to respond to a logic 0 low you
Connect it to the 3.3v rail
One point is if you have the pull-up resistor
To low a value this will set the IN/Put impedance
To low , Ok for noise suppression ,but will degrade
The low input signal,
Regards BoyOh

[mahjongg]

You are given the option of setting the GPIO I/P
To a impedance level that the processor can
Respond to. In its high impedance state floating
It will not sink or source a working level signal
This being a logic level 0 low or 1 high, So you
MUST set it to a working impedance level by
Setting the internal resistance 50k or using a
External resister of 10k . If you want it to respond
To a logic 1 high you connect it to the 0v rail
If you want it to respond to a logic 0 low you
Connect it to the 3.3v rail
One point is if you have the pull-up resistor
To low a value this will set the IN/Put impedance
To low , Ok for noise suppression ,but will degrade
The low input signal,
Regards BoyOh

This post is almost unreadable, due to irregular use of line breaks! Please don't post from a mobile device, or use a different editor to upload texts.

[mahjongg]

I've come across this method for protecting inputs with resistors (full article here https://www.digikey.com/en/articles/tec ... lectronics. Description says that this setup is actually simple voltage divider, but I'm unable to grasp how exactly this corelate to basic voltage divider diagram, which resistor is R1 and which is R2


Basic voltage divider diagram I'm talking about


If I understand correctly, R1 would be 100K resistor, connected as pull-up to 5V, and R2 would be 1K that goes to the switch?

I'm asking all this in order to learn, but also as option to protect my input GPIOs with DHT11 and DS18B20 on them. There are 4.7K pull-up resistors to 3.3V, what size serial resistor should I add in order make it work? Would this even work in my scenario?

Two comments:

The RPI DOES NOT HAVE INPUT PROTECTION DIODES!

and the pullup to 5V is WRONG!
It should be a pulldown to GND.



The circuit should make sure no voltages larger than 3V3 appear on a GPIO.
Rule 101 is that the RPI is NOT 5V tolerant!

Voltages one diode forward drop over 3V3 can cause a fatal latchup condition, even with minimal current.

[PeterO]

The RPI DOES NOT HAVE INPUT PROTECTION DIODES!

Do you mean "external to the SoC" ?
Without any (i.e. even internal ones) I think the GPIO pins would be susceptible (well more susceptible than the seem to be) to Electro Static Discharge ?
PeterO

[boyoh]

You are given the option of setting the GPIO I/P
To a impedance level that the processor can
Respond to. In its high impedance state floating
It will not sink or source a working level signal
This being a logic level 0 low or 1 high, So you
MUST set it to a working impedance level by
Setting the internal resistance 50k or using a
External resister of 10k . If you want it to respond
To a logic 1 high you connect it to the 0v rail
If you want it to respond to a logic 0 low you
Connect it to the 3.3v rail
One point is if you have the pull-up resistor
To low a value this will set the IN/Put impedance
To low , Ok for noise suppression ,but will degrade
The low input signal,
Regards BoyOh

This post is almost unreadable, due to irregular use of line breaks! Please don't post from a mobile device, or use a different editor to upload texts.

Point Taken,,,,,,,,,,, There are some who are better talking about it Than doing It

There are some who are better writing about it Than doing it

Then there are some who are better at doing it Than talking and writing about itt

[mahjongg]

The RPI DOES NOT HAVE INPUT PROTECTION DIODES!

Do you mean "external to the SoC" ?
Without any (i.e. even internal ones) I think the GPIO pins would be susceptible (well more susceptible than the seem to be) to Electro Static Discharge ?
PeterO

I mean internal, and certainly there are no external ones either.

The canonical source of this information is the BCM2835-ARM-Peripherals.pdf page 89 figure 6-1 "GPIO Block Diagram" which does NOT show protection diodes, and in fact if you put more that 3V3 plus the forward voltage of a diode onto a GPIO, current doesn't seem to flow into the 3V3 supply, but instead causes a latch-up!

Also, if there were protecton diodes, it would not be a good protection for an electrostatic discharge, as the currents that could potentially flow from such a discharge could reach hundreds of amperes, enough to instantly vaporise any internal small diode in the SoC.

A disadvantage of protection diodes in a GPIO interface (instead of just a CMOS IC) it that if the 3V3 would fail, then voltages on GPIO pins would start to have a conducting path into the RPI's 3V3 supply rail, and that would mean unwanted current flows into GPIO pins. currents, that might be only limited by the ability of the 3V3 rail to absorb them.

[neilgl]

I quite like his old fashioned format?

[PeterO]

The RPI DOES NOT HAVE INPUT PROTECTION DIODES!

Do you mean "external to the SoC" ?
Without any (i.e. even internal ones) I think the GPIO pins would be susceptible (well more susceptible than the seem to be) to Electro Static Discharge ?
PeterO

I mean internal, and certainly there are no external ones either.

The canonical source of this information is the BCM2835-ARM-Peripherals.pdf page 89 figure 6-1 "GPIO Block Diagram" which does NOT show protection diodes, and in fact if you put more that 3V3 plus the forward voltage of a diode onto a GPIO, current doesn't seem to flow into the 3V3 supply, but instead causes a latch-up!

If it required 3V3 PLUS a diode drop it suggests there is a diode in there somewhere, but maybe not connected to the right thing for it to be considered as a protection diode

Also, if there were protecton diodes, it would not be a good protection for an electrostatic discharge, as the currents that could potentially flow from such a discharge could reach hundreds of amperes, enough to instantly vaporise any internal small diode in the SoC.

Eh ? I'm just about old enough to remember early CMOS devices that didn't have any protection diodes and thus they were VERY susceptible to ESD damage.

A disadvantage of protection diodes in a GPIO interface (instead of just a CMOS IC) it that if the 3V3 would fail, then voltages on GPIO pins would start to have a conducting path into the RPI's 3V3 supply rail, and that would mean unwanted current flows into GPIO pins. currents, that might be only limited by the ability of the 3V3 rail to absorb them.

If the 3V3 fails then I would say "all bets are off". I think you've got you argument the wrong way round. Surely the currents into the GPIO pins would be no greater than the failed 3V3 regulator was providing anyway, so I don't understand what you mean by "the ability of the 3V3 rail to absorb them".

This page seems to have some useful info that has been (as it says) "pieced together" from various places.
http://www.mosaic-industries.com/embedd ... ifications


PeterO

[seandepagnier]

I have been using a similar circuit to protect the uart.

There is a 2.4k resistor from tx. This resistor goes to two diodes similar to the picture above, one to gnd the other to 3v3. The same circuit is used for rx.

This is all I am using for now, no pullups. I'm thinking of adding a second resistor after the diodes.

In either case, I believe it is still susceptible to the "latch up" since the input voltage can still reach 3.3 + diode drop. I don't really care if in this case the pi must reset, but I'm wondering can it do other damage?

Has anyone created the latch up state? What happens? At what voltage does it occur? What is the minimum resistance to prevent damage.


I think the 20 meg ohm resistor in the original post is too high, even 1meg ohm might be too much depending on the situation.

[seandepagnier]

I have been using a similar circuit to protect the uart.

There is a 2.4k resistor from tx. This resistor goes to two diodes similar to the picture above, one to gnd the other to 3v3. The same circuit is used for rx.

This is all I am using for now, no pullups. I'm thinking of adding a second resistor after the diodes.

In either case, I believe it is still susceptible to the "latch up" since the input voltage can still reach 3.3 + diode drop. I don't really care if in this case the pi must reset, but I'm wondering can it do other damage?

Has anyone created the latch up state? What happens? At what voltage does it occur? What is the minimum resistance to prevent damage.


I think the 20 meg ohm resistor in the original post is too high, even 1meg ohm might be too much depending on the situation.

[PeterO]

I think the 20 meg ohm resistor in the original post is too high, even 1meg ohm might be too much depending on the situation.

The 20MΩ resistor isn't a real component. It's there to represent the fact that the logic circuits inside the SoC are not perfect and do take a small amount of current when you apply 3V3 to a pin. (Somewhere there's a longer thread about this from a few weeks ago.)

PeterO

[mahjongg]

This page seems to have some useful info that has been (as it says) "pieced together" from various places.
http://www.mosaic-industries.com/embedd ... ifications


PeterO

Yeah, I knew that source, it is not the primary source, but based on "best guess" information from many sources, and they also mention that the diodes are not real, but formed by (parasitic) internal structures in the chip.

The internal diodes shown in the figure are not really substrate diodes, but they are actually parasitic FETs. Electrically, their I-V characteristic looks like a diode's, but with a greater forward drop and a more gradual knee. They may protect against low current transient events caused by transient out-of-range voltages applied to the pins, but they are not intended to protect against the application of voltages greater than the supply voltage or less than ground, even with an external series resistor. In brief, you should never deliberately forward bias those "diodes". Consequently, you can not safely place an external pull-up resistor to 5V on the I/O pin. That would forward bias a parasitic FET and owing to its poor internal impedance to the chip's internal power rail it may overheat, or worse, it may bias up parts of the chip to voltages greater than they can handle. So, don't do it!

The current flowing into the GPIO ports acts like current flowing into a parasitic thyristor circuit, and can "trigger" that internal structure.

see wikipedia "latch up". https://en.wikipedia.org/wiki/Latch-up