blippy
Posts: 69
Joined: Fri Nov 03, 2017 3:07 pm

Is DMA memory "atomic"?

Tue Jul 14, 2020 7:57 am

This question isn't Pi specific, it's more of a general question about DMA. I'm a noob to the concept of DMA, so bear with me. It's difficult to know where to ask such a question, though.

Suppose an MCU implements an ADC, for example. My understanding is that it takes several clock cycles for the MCU to take a reading. It is possible to set up a DMA so that the reading can be put to a memory address. Let's say that the DMA can put a reading there whenever it wants, and continuously updates the contents of the address.

The question is: ignoring latency issues, is the contents of the memory guaranteed to be a "fully formed" reading, and not some value at an "intermediate" state? In other words, can I just read it whenever I want, and know that the reading is "fully formed"?

I guess the same question applies to generating an interrupt on ADC conversion completion instead of DMA. In this case, my understanding is that the MCU will have a fixed address for the reading. But doesn't that reading start to get refreshed immediately? Meaning that the value I read from the address will be wrong?

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joan
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Location: UK

Re: Is DMA memory "atomic"?

Tue Jul 14, 2020 8:23 am

I would have assumed this is highly specific to the hardware.

You haven't mentioned the data size. I would assume there may be different answers for 8-bit sized, 16-bit sized, 32-bit sized, 64-bit sized data etc.

cleverca22
Posts: 1903
Joined: Sat Aug 18, 2012 2:33 pm

Re: Is DMA memory "atomic"?

Tue Jul 14, 2020 8:27 am

yeah, it will heavily depend on which register and which peripheral your reading

and for most registers, its best to read them as a single 32bit read, or you may run into problems from the value changing between reads

cant really give any further details enless i know which peripheral your asking about, and the pi lacks ADC peripherals

LdB
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Joined: Wed Dec 07, 2016 2:29 pm

Re: Is DMA memory "atomic"?

Tue Jul 14, 2020 12:26 pm

No not atomic in the sense you mean .. large transfers can take milliseconds. That is the point for doing DMA the cpu can go off and do other things while the DMA occurs in the background.
blippy wrote:
Tue Jul 14, 2020 7:57 am
The question is: ignoring latency issues, is the contents of the memory guaranteed to be a "fully formed" reading, and not some value at an "intermediate" state? In other words, can I just read it whenever I want, and know that the reading is "fully formed"?
Generally you don't read anything in the destination until the DMA transfer complete is signaled.
If you just launch a DMA transfer and then go read the destination memory immediately unless the transfer is really small you are pretty much guaranteed to read junk.
So if you have something waiting for a DMA transfer it will be either polling the DMA complete or you will have setup the interrupt.

Look at the DMA control status for each DMA channel and look at bit 1 desription in the data sheet ... the thing to poll.
DMA End Flag, Set when the transfer described by the current control block is complete

If you have the MMU on and multicore access there are other implications in doing some cache management but for the usual single core example you can generally ignore.

The best way to learn is play setup a memory to memory DMA and play around.

blippy
Posts: 69
Joined: Fri Nov 03, 2017 3:07 pm

Re: Is DMA memory "atomic"?

Tue Jul 14, 2020 2:13 pm

LdB wrote:
Tue Jul 14, 2020 12:26 pm
Generally you don't read anything in the destination until the DMA transfer complete is signaled.
If you just launch a DMA transfer and then go read the destination memory immediately unless the transfer is really small you are pretty much guaranteed to read junk.
Ah, thank you!

jayben
Posts: 106
Joined: Mon Aug 19, 2019 9:56 pm

Re: Is DMA memory "atomic"?

Thu Jul 16, 2020 8:09 am

Take a look at my blogs https://iosoft.blog/raspberry-pi-dma-programming/ and https://iosoft.blog/fast-data-capture-raspberry-pi/

Plenty of examples in C to experiment with, but to answer your original question, the DMA controller normally does 32-bit transfers, so any one of the transferred 32-bit values is atomic. So you can check the destination buffer at any time to see what has been transferred into it; however, caching is a major issue, see the blogs for an explanation why.

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