Is it possible to map the PCIe outbound window (base address for requests from CPU to PCIe) to an address below 4GiB, ie to a 32-bit address?
I know that linux maps the window at 0x600000000, which requires LPAE on arm32. I'm working on PCIe support for Plan 9 on arm32, which doesn't use LPAE. I've tried mapping the window at 0x80000000 for example (on a 2GiB pi4), or at 0xFBF00000 (sacrificing 1MiB of ram on a 4GiB pi4), but neither seems to work (usb3 controller registers in the PCIe window just read as zeroes).
Even on an arm64 variant of Plan 9, it appears that mapping the PCIe outbound window at 0x600000000 works but 0x80000000 does not.
Is there something in the Raspberry Pi memory architecture which restricts the configured PCIe window addresses to be >4GiB?