Used ARM Cortex A53 manual to get coprocessor operations. The incrementation of 0x40 made sense to me because the data cache is 4-way set associative (according to the manual and contents of CCSIDR register) and 16 words * 4 cache lines = 64 (0x40). I'm calling the function before each DMA transfer -- no luck. How can I get the USB back up with MMU enabled? I'm wondering if it's a coherency/DMA issue or something else to do with the MMU.
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MOV r0, #0 ;@ Start at zero cloop: MCR p15, 0, r0, c7, c10, 2 ;@ Clean and flush the line by set/way (assuming r0 is the correct cache line index) ADD r0, r0, #0x40 ;@ Increment by 64 bytes (line is 16 words, 16*4=64 bytes) CMP r0, #0x3F000000 ;@ Stop at peripherals BNE cloop ;@ If not branch back to cloop
Worth noting that the memory translation tables are setup according to page 23 of this document (0x00015C06 is crucial):
http://infocenter.arm.com/help/topic/co ... essors.pdf