quick update, working on an example
It appears to me that the gpu is using compare registers C0 and C2. (the gpu firmware I am using is weeks old, things can always change). Using my uart examples as a baseline I had a program print out the timer and the four compare registers. you can see the compare registers changing. as described in the manual the way to use these is to have the isr move the compare register value out in front of the timer. the polling and printing through the uart is quite slow compare do the timer but it is enough to see that when the timer passes the compare register the compare register moves forward for these two, the gpu must be doing this.
as implied in the manual there is no enable control in the system timer itself, the status bits are then assumed to be tied directly to interrupts. which interrupts? by changing the program to enable all interrupts (write 0xFFFFFFFF to 0x210 and 0x214), have some code read the current time, add some (I added 0x00400000) and write that to the compare register 1 and/or compare register 3, then go into an infinite loop printing out the pending status registers (0x204 and 0x208) you see that compare 1 is tied to irq 1 and compare 3 tied to irq3 (bits 1 and 3 in 0x204).
The last step is clearing the interrupt, the docs say to write a one to the status register to clear, if you do this, and then read back both the status register and the interrupt status you see the flag and the interrupt do clear with a write of a 1. I had triggered both c1 and c3 interrupts but only wrote to one of the flag bits (wrote a 2) only that one interrupt cleared. so it seems that the write 1 to clear in the docs is correct.