I have a weird problem - when booting in EL3 I can't seem to be able to enable coherency between cores.
I have two boot settings:
- in the first I boot in EL2 (classical)
- in the second I boot in EL3
In both cases, the configuration for EL2 and EL1 is exactly the same,
both for MMU and for processor registers. When booting in EL3 I spend
only little time in EL3 - I simply configure cptr_el3 and scr_el3 before
entering EL2 (I perform no cache/MMU configuration).
However, in the end, when I start in EL2 memory ends up (after config)
coherent, whereas when I start in EL3 I end up in a state where caches
seem to be on, but non-coherent. I always have to perform explicit cache
operations (cleans and invalidates) in order to communicate.
Do any of you have an idea of what happens ? I'm really at my wits' end.