I want to be sure about some details before starting to code
some interrupt-related stuff. Can you please tell me if the following
assumptions I make are correct? Even partial answers will help me.
1. The RPI3 inherits most of the memory-mapped SoC
peripherals of the RPi1, with the difference that the base
address is now 0x3F000000 (the offsets are preserved).
For instance, the mailboxes 0 and 1 are at address
2. From the document QA7_rev3.4.pdf I understand that
on the RPi3 one separates "GPU peripheral access" from
"Local peripherals". The former seems to follow the offsets
of the RPi1. The latter includes ARM timer, IRQs, etc. and
is totally different from that of the RPi1 (it's actually the
same as the one of the RPi2).
3. One particular point of this "Local peripherals" address
range (starting at 0x40000000) is that it defines a new set of
mailboxes, used only for communcation between ARM cores.
4. Acceeding to these new mailboxes doesn't even reach the
5. The form of mailbox requests (at least part of them) changed.
For instance, MAILBOX_TAG_GET_MAX_CLOCK_RATE now
takes two more arguments of type uint32_t (I know this
https://github.com/raspberrypi/firmware ... -interface
with the code of function ARM_setmaxspeed in this file
https://github.com/LdB-ECM/Raspberry-Pi ... artStart.c
Do you have some document describing the changes in