zeoneo
Posts: 67
Joined: Sun Sep 30, 2018 6:54 am

Need debugging help for setting up paging/VMSAv8-32 on RPI 3B (32 bit)

Mon Dec 31, 2018 4:50 pm

Hi guys I have been trying to enable paging on my RPI 3B in 32 bit mode. I have followed dwelch67 tutorial and then read ARM ARM, TRM about how to do it.

I store First level descriptors starting from 0x4000 which is 16KB aligned. I am using short descriptor format. Manager domain.

When I map VA to PA as shown below paging works

Code: Select all

#include <kernel/virtmem.h>
#include <kernel/uart0.h>

void initialize_virtual_memory(void)
{
    unsigned int ra;
    for (ra = 0;; ra += 0x00100000)
    {
        mmu_section(ra, ra, 0x0000);
        if (ra == 0xFFF00000)
            break;
    }

    // Mapping first 1MB should be sufficient
    // mmu_section(0x00000000, 0x00000000, 0x0000);
    // mmu_section(0x00100000, 0x00000000, 0x0000);

    //peripherals
    mmu_section(0x3f000000, 0x3f000000, 0x0000); //NOT CACHED!
    mmu_section(0x3f200000, 0x3f200000, 0x0000); //NOT CACHED!

    printf("Enabling MMU \n ");
    start_mmu(MMUTABLEBASE, 0x00800001);
}

unsigned int mmu_section(unsigned int vadd, unsigned int padd, unsigned int flags)
{
    unsigned int table1EntryOffset;
    unsigned int table1EntryAddress;
    unsigned int tableEntry;

    table1EntryOffset = (vadd >> 20) << 2; // get only most significant 12 bits
    //and multiply it by 4 as each entry is 4 Bytes 32bits

    // MMU table base should be at 16KB granularity, Least signficant 12 bits will be always 0. hence do OR with that
    table1EntryAddress = MMUTABLEBASE | table1EntryOffset;

    // 31: 20  12 bits are physical 12 ms bits from physical address
    tableEntry = (padd & 0xFFF00000);

    // entry[1:0] = 0b10 for section entry
    tableEntry = tableEntry | 2;

    // Access permissions should be 11 for full access entry [11:10] = 0b11
    tableEntry = tableEntry | 0xC00;

    //hexstrings(rb); hexstring(rc);
    // printf("\n entryAddr: 0x%x, entry value:0x%x \n", table1EntryAddress, tableEntry);
    PUT32(table1EntryAddress, tableEntry);
    return (0);
}


But my kernel is not that big I don't think I need to map everything as of now.

kernel end address __end = 0x15000

I think following code should be sufficient as all the accesses lies in first 1MB from 0x0000, but it doesn't work and it throws prefetch exception.

Code: Select all

void initialize_virtual_memory(void)
{
    // unsigned int ra;
    // for (ra = 0;; ra += 0x00100000)
    // {
    //     mmu_section(ra, ra, 0x0000);
    //     if (ra == 0xFFF00000)
    //         break;
    // }

    // Mapping first 1MB should be sufficient
    mmu_section(0x00000000, 0x00000000, 0x0000);
    mmu_section(0x00100000, 0x00000000, 0x0000);

    //peripherals
    mmu_section(0x3f000000, 0x3f000000, 0x0000); //NOT CACHED!
    mmu_section(0x3f200000, 0x3f200000, 0x0000); //NOT CACHED!

    printf("Enabling MMU \n ");
    start_mmu(MMUTABLEBASE, 0x00800001);
}


Prefetch exception handler from dwelch67/mmu prints
last value of R0 = 0000A1E0
DFSR= 000008A7 => [2:0] = 0b111 => translation fault page from manual.
IFSR= 00001629
lr = 00008700
instruction = E92D4010 => e92d4010 push {r4, lr}
00008040

Code: Select all

data_abort_vector_asm:
    mov r6,lr
    ldr r8,[r6,#-8]
    mrc p15,0,r4,c5,c0,0 ;@ data/combined
    mrc p15,0,r5,c5,c0,1 ;@ instruction
    mov sp,#0x00004000
    bl hexstrings
    mov r0,r4
    bl hexstrings
    mov r0,r5
    bl hexstrings
    mov r0,r6
    bl hexstrings
    mov r0,r8
    bl hexstrings
    mov r0,r7
    bl hexstrings
123:
    b 123b
    


For reference I have attached all relevant code here.

-----Boot.S---------

Code: Select all

// To keep this in the first portion of the binary.
.section ".text.boot"
 
// Make _start global.
.globl _start
.global _get_stack_pointer
.global _exception_table
.global _enable_interrupts

.equ ARM_MODE_USR, 0x10;								;@ CPU in USR mode .. Normal User mode
.equ ARM_MODE_FIQ, 0x11;								;@ CPU in FIQ mode .. FIQ Processing
.equ ARM_MODE_IRQ, 0x12;								;@ CPU in IRQ mode .. IRQ Processing
.equ ARM_MODE_SVC, 0x13;								;@ CPU in SVC mode .. Service mode
.equ ARM_MODE_HYP, 0x1A;								;@ CPU in HYP mode .. Hypervisor mode  (ARM7/ARM8 only)
.equ ARM_MODE_UND, 0x1B;								;@ CPU in UND mode .. Undefined Instructions mode
.equ ARM_MODE_SYS, 0x1F;	

.equ ARM_MODE_MASK, 0x1F;								;@ Mask to clear all but CPU mode bits from cpsr register
.equ ARM_I_BIT,		0x80;								;@ IRQs disabled when set to 1
.equ ARM_F_BIT,		0x40;

.equ    CPSR_MODE_USER,         0x10
.equ    CPSR_MODE_FIQ,          0x11
.equ    CPSR_MODE_IRQ,          0x12
.equ    CPSR_MODE_SVR,          0x13
.equ    CPSR_MODE_ABORT,        0x17
.equ    CPSR_MODE_UNDEFINED,    0x1B
.equ    CPSR_MODE_SYSTEM,       0x1F

// See ARM section A2.5 (Program status registers)
.equ    CPSR_IRQ_INHIBIT,       0x80
.equ    CPSR_FIQ_INHIBIT,       0x40
.equ    CPSR_THUMB,             0x20

.equ	SCTLR_ENABLE_DATA_CACHE,        0x4
.equ	SCTLR_ENABLE_BRANCH_PREDICTION, 0x800
.equ	SCTLR_ENABLE_INSTRUCTION_CACHE, 0x1000


.balign 4

_start:
    ldr pc, _reset_h
    ldr pc, _undefined_instruction_vector_h
    ldr pc, _software_interrupt_vector_h
    ldr pc, _prefetch_abort_vector_h
    ldr pc, _data_abort_vector_h
    ldr pc, _unused_handler_h
    ldr pc, _interrupt_vector_h
    ldr pc, _fast_interrupt_vector_h

	_reset_h:                           .word   _reset_
	_undefined_instruction_vector_h:    .word   undefined_instruction_vector
	_software_interrupt_vector_h:       .word   software_interrupt_vector
	_prefetch_abort_vector_h:           .word   prefetch_abort_vector
	_data_abort_vector_h:               .word   data_abort_vector_asm
	_unused_handler_h:                  .word   _reset_
	_interrupt_vector_h:                .word   irq_handler_asm_wrapper
	_fast_interrupt_vector_h:           .word   fast_interrupt_vector


_reset_:
    mrc p15, 0, r6,c0,c0,5
    and     r6, r6, #3
    mov r7, #0
    cmp     r6, r7
    beq 2f
    // cpu id > 0, stop
1:  wfe
    b       1b
2:  // cpu id == 0


	mov r12, pc											;@ Hold boot address in high register R12
	mrs r0, CPSR										;@ Fetch the cpsr register
	orr r0, r0, #(ARM_I_BIT | ARM_F_BIT)				;@ Disable Irq/Fiq
	and r11, r0, #ARM_MODE_MASK							;@ Clear all but CPU mode bits in register r11

 	cmp r11, #ARM_MODE_HYP								;@ Check we are in HYP_MODE											
	bne .NotInHypMode									;@ Branch if not equal meaning was not in HYP_MODE  
	bic r0, r0, #ARM_MODE_MASK							;@ Clear the CPU mode bits in register r0							
	orr r0, r0, #ARM_MODE_SVC							;@ ARM_MODE_SVC bits onto register	
    msr spsr_cxsf,r0									;@ Hold value in spsr_cxsf
    add lr,pc,#4										;@ Calculate address of .NotInHypMode label

	msr ELR_hyp, lr
	eret

.NotInHypMode:
    mov r0,#0x8000
    mov r1,#0x0000
    ldmia r0!,{r2,r3,r4,r5,r6,r7,r8,r9}
    stmia r1!,{r2,r3,r4,r5,r6,r7,r8,r9}
    ldmia r0!,{r2,r3,r4,r5,r6,r7,r8,r9}
    stmia r1!,{r2,r3,r4,r5,r6,r7,r8,r9}

    ;@ (PSR_IRQ_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS)
    mov r0,#0xD2
    msr cpsr_c,r0
    mov sp,#0x3000

    ;@ (PSR_FIQ_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS)
    ;@mov r0,#0xD1
    ;@msr cpsr_c,r0
    ;@mov sp,#0x000

    ;@ (PSR_SVC_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS)
    mov r0,#0xD3
    msr cpsr_c,r0
    mov sp,#0x8000000

    // enable unaligned address access
	mrc p15, 0, r0, c1, c0, 0
	orr r0, #1 << 22
	mcr p15, 0, r0, c1, c0, 0

    // Enable VFP ------------------------------------------------------------

    // r1 = Access Control Register
    MRC p15, #0, r1, c1, c0, #2
    // enable full access for p10,11
    ORR r1, r1, #(0xf << 20)
    // ccess Control Register = r1
    MCR p15, #0, r1, c1, c0, #2
    MOV r1, #0
    // flush prefetch buffer because of FMXR below
    MCR p15, #0, r1, c7, c5, #4
    // and CP 10 & 11 were only just enabled
    // Enable VFP itself
    MOV r0,#0x40000000
    // FPEXC = r0
    FMXR FPEXC, r0


	// Call clear-bss.c
	bl _clear_bss

 
	// halt
_inf_loop:
    b       _inf_loop

.globl PUT32
PUT32:
    str r1,[r0]
    bx lr

.globl GET32
GET32:
    ldr r0,[r0]
    bx lr

.globl dummy
dummy:
    mov     pc, lr

.globl enable_irq
enable_irq:
    mrs r0,cpsr
    bic r0,r0,#0x80
    msr cpsr_c,r0
    bx lr

_get_stack_pointer:
    // Return the stack pointer value
    str     sp, [sp]
    ldr     r0, [sp]

    // Return from the function
    mov     pc, lr


_enable_interrupts:
    mrs     r0, cpsr
    bic     r0, r0, #0x80
    msr     cpsr_c, r0
    mov     pc, lr

irq_handler_asm_wrapper:
    sub     lr, lr, #4
    srsdb   sp!, #0x13
    cpsid   if, #0x13
    push    {r0-r3, r12, lr}
    and     r1, sp, #4
    sub     sp, sp, r1
    push    {r1}
    bl      irq_handler
    pop     {r1}
    add     sp, sp, r1
    pop     {r0-r3, r12, lr}
    rfeia   sp!

.globl start_mmu
start_mmu:
    mov r2,#0
    mcr p15,0,r2,c8,c7,0 ;@ invalidate tlb
    mcr p15,0,r2,c7,c10,4 ;@ DSB ??

     ;@ Domain 0 Manager access. No permissions checked for access
    MRC p15, 0, r2, c3, c0, 0 ;@ Read DACR into Rt
    ORR r2, #3
    MCR p15, 0, r2, c3, c0, 0 ;@ Write Rt to DACR

    MCR p15,0,r0,c2,c0,0 ;@ Write Rt to TTBR0
    MCR p15, 0, r0, c2, c0, 1 ;@ Write Rt to TTBR1

    MRC p15, 0, r2, c1, c0, 0 ;@ Read SCTLR into Rt
    orr r2,r2,r1
    MCR p15, 0, r2, c1, c0, 0 ;@ Write Rt to SCTLR.

    bx lr

data_abort_vector_asm:
    mov r6,lr
    ldr r8,[r6,#-8]
    mrc p15,0,r4,c5,c0,0 ;@ data/combined
    mrc p15,0,r5,c5,c0,1 ;@ instruction
    mov sp,#0x00004000
    bl hexstrings
    mov r0,r4
    bl hexstrings
    mov r0,r5
    bl hexstrings
    mov r0,r6
    bl hexstrings
    mov r0,r8
    bl hexstrings
    mov r0,r7
    bl hexstrings
123:
    b 123b

.globl stop_mmu
stop_mmu:
    mrc p15,0,r2,c1,c0,0
    bic r2,#0x1000
    bic r2,#0x0004
    bic r2,#0x0001
    mcr p15,0,r2,c1,c0,0
    bx lr

.globl invalidate_tlbs
invalidate_tlbs:
    mov r2,#0
    mcr p15,0,r2,c8,c7,0  ;@ invalidate tlb
    mcr p15,0,r2,c7,c10,4 ;@ DSB ??
    bx lr

.globl read_cpu_id
read_cpu_id:
    // read cpu id, stop slave cores
    // mrc p15, 0, r0, c0, c0, 0
    mrc p15, 0, r0,c0,c0,5
    bx lr

-----------virtual_mem.c---------

Code: Select all

#include <kernel/virtmem.h>
#include <kernel/uart0.h>

void initialize_virtual_memory(void)
{
    // unsigned int ra;
    // for (ra = 0;; ra += 0x00100000)
    // {
    //     mmu_section(ra, ra, 0x0000);
    //     if (ra == 0xFFF00000)
    //         break;
    // }

    // Mapping first 1MB should be sufficient
    mmu_section(0x00000000, 0x00000000, 0x0000);
    mmu_section(0x00100000, 0x00000000, 0x0000);

    //peripherals
    mmu_section(0x3f000000, 0x3f000000, 0x0000); //NOT CACHED!
    mmu_section(0x3f200000, 0x3f200000, 0x0000); //NOT CACHED!

    printf("Enabling MMU \n ");
    start_mmu(MMUTABLEBASE, 0x00800001);
}

unsigned int mmu_section(unsigned int vadd, unsigned int padd, unsigned int flags)
{
    unsigned int table1EntryOffset;
    unsigned int table1EntryAddress;
    unsigned int tableEntry;

    table1EntryOffset = (vadd >> 20) << 2; // get only most significant 12 bits
    //and multiply it by 4 as each entry is 4 Bytes 32bits

    // MMU table base should be at 16KB granularity, Least signficant 12 bits will be always 0. hence do OR with that
    table1EntryAddress = MMUTABLEBASE | table1EntryOffset;

    // 31: 20  12 bits are physical 12 ms bits from physical address
    tableEntry = (padd & 0xFFF00000);

    // entry[1:0] = 0b10 for section entry
    tableEntry = tableEntry | 2;

    // Access permissions should be 11 for full access entry [11:10] = 0b11
    tableEntry = tableEntry | 0xC00;

    //hexstrings(rb); hexstring(rc);
    // printf("\n entryAddr: 0x%x, entry value:0x%x \n", table1EntryAddress, tableEntry);
    PUT32(table1EntryAddress, tableEntry);
    return (0);
}

-----linker.ld----

Code: Select all

ENTRY(_start)
 
SECTIONS
{
    /* Starts at LOADER_ADDR. */
    . = 0x8000;
    __start = .;
    __text_start = .;
    .text :
    {
        KEEP(*(.text.boot))
        *(.text)
    }
    . = ALIGN(4096); /* align to page size */
    __text_end = .;
 
    __rodata_start = .;
    .rodata :
    {
        *(.rodata)
    }
    . = ALIGN(4096); /* align to page size */
    __rodata_end = .;
 
    __data_start = .;
    .data :
    {
        *(.data)
    }
    . = ALIGN(4096); /* align to page size */
    __data_end = .;
 
    __bss_start = .;
    .bss :
    {
        bss = .;
        *(.bss)
    }
    . = ALIGN(4096); /* align to page size */
    __bss_end = .;
    __end = .;
}

Please help me debug this issue. I have no clue why this is happening. I tried checking if I am correctly in SVC mode which provides RW access to registers like DACR, TTBR0, TTBR1, TTBCR. SCTLR.

Thanks in advance...!
Let there be some light .../\...

zeoneo
Posts: 67
Joined: Sun Sep 30, 2018 6:54 am

Re: Need debugging help for setting up paging/VMSAv8-32 on RPI 3B (32 bit)

Wed Jan 02, 2019 3:25 am

@LdB you seem to have implemented paging in AARCH64 mode would you be able to point in some direction sir?
Let there be some light .../\...

LdB
Posts: 1283
Joined: Wed Dec 07, 2016 2:29 pm

Re: Need debugging help for setting up paging/VMSAv8-32 on RPI 3B (32 bit)

Wed Jan 02, 2019 6:57 am

Happy new year all.

Hmm looking at your code .. strange thing what is all the initial code about parking cores doing in startup the cores will never be released by the boot stub. I don't get that but moving on.

Not understanding the bit23 of the value 0x00800001 .. and you have not turned the cache on (bit 2) :-)

Code: Select all

start_mmu(MMUTABLEBASE, 0x00800001);
If you follow start_mmu the second variable goes in as r1 and ends up ORR'ed here from what I can tell

Code: Select all

    MRC p15, 0, r2, c1, c0, 0 ;@ Read SCTLR into Rt
    orr r2,r2,r1 /* 0x00800001 ends up orr'ed here */
    MCR p15, 0, r2, c1, c0, 0 ;@ Write Rt to SCTLR.
This might help for the SCTLR register ... I don't even have a definition for bit 23 so I have no idea what that does and pretty sure you need bit 2 on as well as bit 0 :-)
Arm site is doing maintenance so I can't even look it up.

Code: Select all

#define SCTLR_M            (1 << 0)	/* Bit 0:  MPU enable bit */
#define SCTLR_A            (1 << 1)	/* Bit 1:  Enables strict alignment of data */
#define SCTLR_C            (1 << 2)	/* Bit 2:  Determines if data can be cached */
/* Bits 3-4: Reserved */
#define SCTLR_CCP15BEN     (1 << 5)	/* Bit 5:  CP15 barrier enable */
/* Bit 6:  Reserved */
#define SCTLR_B            (1 << 7)	/* Bit 7:  Should be zero on ARMv7-R */
/* Bits 8-9: Reserved */
#define SCTLR_SW           (1 << 10)	/* Bit 10: SWP/SWPB Enable bit */
#define SCTLR_Z            (1 << 11)	/* Bit 11: Program flow prediction control */
#define SCTLR_I            (1 << 12)	/* Bit 12: Determines if instructions can be cached */
#define SCTLR_V            (1 << 13)	/* Bit 13: Vectors bit */
#define SCTLR_RR           (1 << 14)	/* Bit 14: Cache replacement strategy */
/* Bits 15-16: Reserved */
#define SCTLR_BR           (1 << 17)	/* Bit 17: Background Region bit */
/* Bit 18: Reserved */
#define SCTLR_DZ           (1 << 19)	/* Bit 19: Divide by Zero fault enable bit */
/* Bit 20: Reserved */
#define SCTLR_FI           (1 << 21)	/* Bit 21: Fast interrupts configuration enable bit */
#define SCTLR_U            (1 << 22)	/* Bit 22: Unaligned access model (always one) */
#define SCTLR_VE           (1 << 24)	/* Bit 24: Interrupt Vectors Enable bit */
#define SCTLR_EE           (1 << 25)	/* Bit 25: Determines the value the CPSR.E */
#define SCTLR_NMFI         (1 << 27)	/* Bit 27: Non-maskable FIQ (NMFI) support */
/* Bits 28-29: Reserved */
#define SCTLR_TE           (1 << 30)	/* Bit 30: Thumb exception enable */
#define SCTLR_IE (1 << 31) /* Bit 31: Instruction endian-ness */
So my guess is you want

Code: Select all

start_mmu(MMUTABLEBASE, 0x00000005);

zeoneo
Posts: 67
Joined: Sun Sep 30, 2018 6:54 am

Re: Need debugging help for setting up paging/VMSAv8-32 on RPI 3B (32 bit)

Wed Jan 02, 2019 7:25 am

Hi,

Thanks for replying. Happy new year to you too :) .
Hmm looking at your code .. strange thing what is all the initial code about parking cores doing in startup the cores will never be released by the boot stub. I don't get that but moving on.
It was pain while debugging with Qemu so I halted them at beginning, will work on that later once paging works :D
Not understanding the bit23 of the value 0x00800001
Yeah it was a mistake, bit 23 is reserved bit according to ARM ARMv-32.

I tried using
start_mmu(MMUTABLEBASE, 0x00000005);
but I got same results on actual hardware and Qemu,

IFSR= 0x1629 = Domain fault.

Am I messing with DACR ? I am trying to point section entries to DOMAIN[0] and I am setting domain[0] = 0b11 ;@ manager access; full access.
Let there be some light .../\...

zeoneo
Posts: 67
Joined: Sun Sep 30, 2018 6:54 am

Re: Need debugging help for setting up paging/VMSAv8-32 on RPI 3B (32 bit)

Fri Jan 04, 2019 6:18 am

@LdB I have found something interesting here.

I do identity mapping as follows then it works

Code: Select all

void initialize_virtual_memory(void)
{
    /* Not needed now 
    unsigned int ra;
    for (ra = 0;; ra += 0x00100000)
    {
        mmu_section(ra, ra, 0x0000);
        if (ra == 0x08000000)
            break;
    }
    */

    // This mapping works.
    mmu_section(0x00000000, 0x00000000, 0x0000);

    // Still need to figure out why I need to map following
    mmu_section(0x07f00000, 0x07f00000, 0x0000);

    //peripherals
    mmu_section(0x3f000000, 0x3f000000, 0x0000); //NOT CACHED!
    mmu_section(0x3f200000, 0x3f200000, 0x0000); //NOT CACHED!

    uart_puts("Enabling MMU \n ");
    start_mmu(MMUTABLEBASE, 0x00000005);
    uart_puts("After paging \n ");
}


Do you have any idea about

Code: Select all

    mmu_section(0x07f00000, 0x07f00000, 0x0000);
Let there be some light .../\...

LdB
Posts: 1283
Joined: Wed Dec 07, 2016 2:29 pm

Re: Need debugging help for setting up paging/VMSAv8-32 on RPI 3B (32 bit)

Fri Jan 04, 2019 8:07 am

That is a simple 1:1 identity map so you must be using data there?

Where is the table itself. All I can find for the table itself is MMUTABLEBASE which has no value in the code you published. I am guessing it's in virtual_mem.h and I place bets on :-)

Code: Select all

#define MMUTABLEBASE 0x07F00000
.
Personally I would have the table location set in the linker file after the code+data but before the heap or just as a static global variable so it goes in the data section but that is just how I roll (so I know my table is somewhere nice and safe and guaranteed 1:1 mapped).

If not that then run a map of the elf file using "nm" and see what maps to there.

zeoneo
Posts: 67
Joined: Sun Sep 30, 2018 6:54 am

Re: Need debugging help for setting up paging/VMSAv8-32 on RPI 3B (32 bit)

Fri Jan 04, 2019 8:53 am

No I do not have any reference to 0x07F00000 according to nm.

Code: Select all

0000808c t .NotInHypMode
00000040 a ARM_F_BIT
00000080 a ARM_I_BIT
00000011 a ARM_MODE_FIQ
0000001a a ARM_MODE_HYP
00000012 a ARM_MODE_IRQ
0000001f a ARM_MODE_MASK
00000013 a ARM_MODE_SVC
0000001f a ARM_MODE_SYS
0000001b a ARM_MODE_UND
00000010 a ARM_MODE_USR
00000040 a CPSR_FIQ_INHIBIT
00000080 a CPSR_IRQ_INHIBIT
00000017 a CPSR_MODE_ABORT
00000011 a CPSR_MODE_FIQ
00000012 a CPSR_MODE_IRQ
00000013 a CPSR_MODE_SVR
0000001f a CPSR_MODE_SYSTEM
0000001b a CPSR_MODE_UNDEFINED
00000010 a CPSR_MODE_USER
00000020 a CPSR_THUMB
000080e8 T GET32
000080e0 T PUT32
00008458 T RPI_ArmTimerInit
00008430 T RPI_GetArmTimer
00008470 T RPI_GetIrqController
00000800 a SCTLR_ENABLE_BRANCH_PREDICTION
00000004 a SCTLR_ENABLE_DATA_CACHE
00001000 a SCTLR_ENABLE_INSTRUCTION_CACHE
0000a010 d _GLOBAL_OFFSET_TABLE_
0000c000 B __bss_end
0000b000 B __bss_start
0000b000 B __data_end
0000a000 D __data_start
00008220 t __delay_53
00008230 t __delay_70
0000c000 B __end
0000a000 D __rodata_end
00009000 R __rodata_start
00008000 T __start
00009000 R __text_end
00008000 T __text_start
000083d0 T _clear_bss
00008030 t _data_abort_vector_h
00008110 T _enable_interrupts
         U _exception_table
0000803c t _fast_interrupt_vector_h
00008104 T _get_stack_pointer
000080dc t _inf_loop
00008038 t _interrupt_vector_h
0000802c t _prefetch_abort_vector_h
00008040 t _reset_
00008020 t _reset_h
00008028 t _software_interrupt_vector_h
00008000 T _start
000081c4 t _undefined_instruction_vector_asm
00008024 t _undefined_instruction_vector_h
00008034 t _unused_handler_h
0000b000 B bss
0000b000 B count_irqs
00008528 T data_abort_vector
00008180 t data_abort_vector_asm
000080f0 T dummy
000080f4 T enable_irq
000082e4 T hexstrings
00008580 T initialize_virtual_memory
000081e4 T invalidate_tlbs
0000854c T irq_handler
00008120 t irq_handler_asm_wrapper
00008324 T kernel_main
000085fc T mmu_section
00008504 T prefetch_abort_vector
000081f4 T read_cpu_id
00008498 T reset_vector
0000a000 d rpiArmTimer
0000a004 d rpiIRQController
000084dc T software_interrupt_vector
00008150 T start_mmu
000081cc T stop_mmu
00008294 T uart_getc
000081fc T uart_init
00008270 T uart_putc
000082bc T uart_puts
000084bc T undefined_instruction_vector

virt_mem.h --------------

Code: Select all

#ifndef _VIRT_MEM_H
#define _VIRT_MEM_H

#define MMUTABLEBASE 0x00004000

extern void PUT32(unsigned int addr, unsigned int value);
extern unsigned int GET32(unsigned int addr);

extern void start_mmu(unsigned int, unsigned int);
extern void stop_mmu(void);
extern void invalidate_tlbs(void);

void initialize_virtual_memory(void);
unsigned int mmu_section(unsigned int vadd, unsigned int padd, unsigned int flags);
#endif
I don't understand what is causing address reference to 0x07F00000.

gihub link of my minimal paging code is https://github.com/zeoneo/rpi3b-bare-me ... /05-paging
Let there be some light .../\...

zeoneo
Posts: 67
Joined: Sun Sep 30, 2018 6:54 am

Re: Need debugging help for setting up paging/VMSAv8-32 on RPI 3B (32 bit)

Fri Jan 04, 2019 9:34 am

Ohh I got it after lot of debugging its stack pointer I have initialized in boot.S. So stupid

Code: Select all

    ;@ (PSR_SVC_MODE|PSR_FIQ_DIS|PSR_IRQ_DIS)
    mov r0,#0xD3
    msr cpsr_c,r0
    mov sp,#0x8000000

Sorry for trouble and thanks I could debug it with your help.

:D
Let there be some light .../\...

LdB
Posts: 1283
Joined: Wed Dec 07, 2016 2:29 pm

Re: Need debugging help for setting up paging/VMSAv8-32 on RPI 3B (32 bit)

Fri Jan 04, 2019 1:39 pm

Haha historically I have done the same sort of thing and why I also allocate the stack in the linker file as it is much safer .. anyhow all solved :-)

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