jamesmintram
Posts: 31
Joined: Mon Jan 15, 2018 12:14 am

Reasons behind MMIO base address

Sun Sep 09, 2018 9:12 pm

The Pi 2 and 3 have 1024MB of memory from 0x00000000 to 0x3EFFFFFF and use the last 16MB for memory mapped IO (0x3F000000 - 0x3FFFFFFF)

I am curious as to why they didn't just start the MMIO at 0x40000000?

Does anyone know?

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joan
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Location: UK

Re: Reasons behind MMIO base address

Sun Sep 09, 2018 9:21 pm

Perhaps there is no memory to map at that address?

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Ultibo
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Re: Reasons behind MMIO base address

Sun Sep 09, 2018 11:26 pm

jamesmintram wrote:
Sun Sep 09, 2018 9:12 pm
I am curious as to why they didn't just start the MMIO at 0x40000000?
What we have learned from snippets of information provided over the years is that the VC4 GPU only supports a 1GB address space (which is the reason why the Pi cannot have more than 1GB) and because the GPU needs access to the peripherals they need to fall within that 1GB range.

The Pi2 and Pi3 also have a local peripherals (or ARM control) block at 0x40000000 but the GPU doesn't need to access that at all.

The memory located in the 16MB peripherals region is not wasted though, later versions of the firmware allow the GPU to make use of it even though it isn't accessible to the ARM CPUs.
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jamesmintram
Posts: 31
Joined: Mon Jan 15, 2018 12:14 am

Re: Reasons behind MMIO base address

Tue Sep 11, 2018 11:39 am

What we have learned from snippets of information provided over the years is that the VC4 GPU only supports a 1GB address space (which is the reason why the Pi cannot have more than 1GB) and because the GPU needs access to the peripherals they need to fall within that 1GB range.

Ah, that makes sense.

Thanks!

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