In the document QA7_rev3.4.pdf,
section 4.6 states -
The registers allow you to enable or
disable an IRQ or FIQ interrupt. They cannot clear an pending interrupts. For that and other details of the
timers, read the Cortex-A7-coprocessor description.
In the Armv7 architecture reference manual (issue c.d) , section B8.1, page b8-1954 says this -
In the timer control register CNTP_CTL, CNTHP_CTL, or CNTV_CTL:
— The timer is enabled.
— The timer output signal is not masked.
This means that, to deassert the timer output signal, software must do one of the following:
• Reprogram the timer registers so that neither of the timer conditions is met.
• Mask the timer output signal, in the timer control register.
• Disable the timer, in the timer control register.
So if i program CNTP_CTL & CNTP_TVAL , and lets say i program one of the core 0 timer registers for interrupts, at address 0x4000_0000, i am able to get the interrupts, but i am not able to clear the pending interrupts. Does anyone know how to clear the interrupt pending status for this timer?
Isnt the architected timer supposed to be one-shot (with automatic clearing of the status bit) ?
Linux seems to be overwriting the mask bit (in timer handler function) and also resetting the cntp_tval in set_next_event() function - https://github.com/raspberrypi/linux/bl ... ch_timer.c
Not sure whether this is the right way to do it.
N.B - this is for bare-metal code (linux code is cited only for reference). This is running on a Raspberry pi 2 (cortex a7 version)
Could someone tell the exact way to clear the pending interrupt ?