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What is co-processor and mrc instruction?

Wed Jan 17, 2018 9:42 pm

I have a RPi3 and I am trying out this program - ... ernel7.asm

I could successfully build and run the program. I understood all of the code except the below.

; Return CPU ID (0..3) Of The CPU Executed On
mrc p15,0,r0,c0,c0,5 ; R0 = Multiprocessor Affinity Register (MPIDR)
ands r0,3 ; R0 = CPU ID (Bits 0..1)
bne CoreLoop ; IF (CPU ID != 0) Branch To Infinite Loop (Core ID 1..3)

I understand that this is used to put the 3 cores out of the 4 cores in infinite loop. But I don't understand the mrc instruction. I tried searching online but did not find any beginner documentation.

I have read the below link and understand how to use r0 to r12, sp, lr and pc. ... 128950.htm

On the same site I found this regarding co-processor: ... 137632.htm. I understood there is something which has registers p0 to p15 and c0 to c15. But I have no idea what a co-processor is. Is it the GPU?

Could someone explain or point me to documentation which I should read to understand co-processor and mrc instruction?

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Re: What is co-processor and mrc instruction?

Thu Jan 18, 2018 12:34 am

The ARM architecture (in the 32-bit instruction set) has support for 16 coprocessors (CP0 to CP15) that extend the ARM's functionality, CP15 is for system control, CP14 is for Debug / Thumb / Jazelle support, CP10 & CP11 are for the floating-point / SIMD control, CP0 to CP7 are available for vendors (chip makers) to use, CP8,9,12 & 13 are reserved for ARM (though never used I don't think). The 64-bit instruction set does away with coprocessors but they appear in the A32 compatibility mode.

The ARMv7-arm has a decent section on the use starting in section A2.9 (Official version here, you need to register to download it). The A53-trm also lists what the CP15 registers are here, scroll down a bit to System Control - AARCH32 resgister summary.
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