btauro
Posts: 30
Joined: Fri Jan 12, 2018 3:11 am

Difference between Interrupts in x86 and Exceptions in Arm

Wed Jan 17, 2018 2:22 am

Hi,

I am having a tough time to understand what is exception levels in ARMv8 and its significance when building Page Tables and Interrupt handling.I know we have 4 levels.EL0,EL1,EL2,El3.
  • Is Exception similar to Interrupt handling in X86 .
  • And while building a kernel in ARMv8-A 64 bit do we have to be in EL1 or EL2.
  • Is the Exception Levels a distinct feature to ARM when compared to X86 and do we need to have a separate MMU(Page Translation Mechanism) for each exception level..
Thanks,

LdB
Posts: 708
Joined: Wed Dec 07, 2016 2:29 pm

Re: Difference between Interrupts in x86 and Exceptions in Arm

Wed Jan 17, 2018 3:15 am

The EL on the ARM are the same as the protection ring terminology on Intel only the numbers go backwards it used to always caused me problems when starting out :-)

So on an Intel you have this
Image

If you look at the ARMv8-A 64 documentation, we can sort of assign them.
The ARM has a higher level of security hypervisor not present in the Intel but we can sort of group them like so
EL0 = ring 3
EL1 = ring 2,ring1
EL2 = ring0 + some hypervisor (not on intel model above)
EL3 = secure hypervisor + trustzone (not on intel model above)

I guess it stops having to have ring -1 (Hypervisor) and ring -2 (System hypervisor) on an Intel and so the
ARM terminology has grown on me.
btauro wrote:
Wed Jan 17, 2018 2:22 am
Is Exception similar to Interrupt handling in X86
Exception is just a call to the vector table based on a condition, it is exactly the same on an Intel
Here is the list from your beloved x86 well actually the Intel 386 ... there are more for 486 etc
https://support.microsoft.com/en-us/hel ... exceptions

Same as the Intel you can have the protection mode on or off, which is why we can get away with
not setting up the Page Tables if we leave the protection mode off. So in the x86 you call unprotected
mode real mode I guess you can say the ARM has the same ability to run in a real mode.

My blink the activity LED sample does exactly that it runs an interrupt in what you would call real mode
https://github.com/LdB-ECM/Raspberry-Pi ... /myBlinker
Specifically look at
https://github.com/LdB-ECM/Raspberry-Pi ... tStart64.S
You need to setup the tables and turn the MMU bit on if you want to convert it to protected mode.
btauro wrote:
Wed Jan 17, 2018 2:22 am
And while building a kernel in ARMv8-A 64 bit do we have to be in EL1 or EL2.
You don't have to do anything it's no different to an Intel. That said the chip was designed with an
idea in mind about the protection levels and often registers you may want may not be on the level
you are in if you change them dramatically. It's not an issue you setup a security level swap and
go and hit the register you want.

So the chip was designed around apps run EL0, Interrupt services and device drivers EL1, kernel in EL2
and EL3 being multi-system hypervisor and setup that way you will have access to the registers you
need without having to switch levels. It won't make your system any more secure running things in
higher levels it's as easy/difficult to switch from EL3/2 as it is to switch from EL1/0. There is an
exception with trust-zones in EL3/2 but as I don't know the Intel equivalent lets leave it out of the
scope. So when starting out I suggest you start that way it's the way the linux kernels work and
so when you are looking at linux code it will make sense.
btauro wrote:
Wed Jan 17, 2018 2:22 am
Is the Exception Levels a distinct feature to ARM when compared to X86 and do we need to have a separate MMU(Page Translation Mechanism) for each exception level..
It is near identical to the Intel protection rings, it is sounding like you only have experience with the Intel in Real mode is this the problem?

btauro
Posts: 30
Joined: Fri Jan 12, 2018 3:11 am

Re: Difference between Interrupts in x86 and Exceptions in Arm

Wed Jan 17, 2018 4:43 am

Thank you for helping me out.

Honestly i am just a baby right now in both x86 and ARM world but I always had a passion to build an OS .So I have decided to build at least a minimal kernel for raspberry pi3.

So basically yes I have worked only in real mode.

I still have few questions which i do not know.It would be great if you could help

what is the general approach or structure in which i build interrupt handlers in Arm?

And what do I need to learn in order to have have Paging in ARM?

And Still not clear whether we need to have separate page translation mechanisms for each Exception Level?

Any resources,link will be very helpful

Thanks

dwelch67
Posts: 919
Joined: Sat May 26, 2012 5:32 pm

Re: Difference between Interrupts in x86 and Exceptions in Arm

Wed Jan 17, 2018 9:35 pm

I hate to say it or maybe I dont, probably better off starting with a pi-zero and the ARM 11 than diving into arm with this chip. My two cents...

LdB
Posts: 708
Joined: Wed Dec 07, 2016 2:29 pm

Re: Difference between Interrupts in x86 and Exceptions in Arm

Thu Jan 18, 2018 4:13 am

btauro wrote:
Wed Jan 17, 2018 4:43 am
So basically yes I have worked only in real mode.
Ok so we have some ground to cover.
btauro wrote:
Wed Jan 17, 2018 4:43 am
what is the general approach or structure in which i build interrupt handlers in Arm?
And what do I need to learn in order to have have Paging in ARM?
And Still not clear whether we need to have separate page translation mechanisms for each Exception Level?
Before we get into that we have a problem we need to discuss you have 4 cores on the Pi3, and why David is suggesting you start with the simpler Pi Zero with it's single core !!!!!!

Remember the memory and interrupts are shared with all four cores and so you are talking about setting up memory tables and interrupts but you must first decide how you are going to partition everything.

Now you could just leave 3 cores parked and write it like you are on a Pi-zero that is an option but 3/4 of your Pi3 power will be sitting idle.

So the first question for your O/S is you are going to have some sort of task switcher/despatcher is it going to be multi core aware.
This sets up if the memory table exceptions and interrupts are going to be all handled by one core or are you going to share the load.
I would strongly suggest you start with playing with task switchers in real mode (leave the MMU off) and get that part sorted first, that is my 2 cents.

However if you want to dive in at the deep end Circle64 might be a good place to start and "rst" does comment on here
https://github.com/rsta2/circle64

This is his exception and interrupt code
https://github.com/rsta2/circle64/blob/ ... tionstub.S
The translation table
https://github.com/rsta2/circle64/blob/ ... ntable.cpp
You might also like to use his level struct definitions from since he has done it for you :-)
https://github.com/rsta2/circle64/blob/ ... armv8mmu.h

I don't know much about his code as it's c++ which for my work is a drop dead because I only have C support for many processors I work on. However a quick look says to me he is handling all the interrupts and exceptions on core0 but it looks like it is setup they could be passed to any core from
https://github.com/rsta2/circle64/blob/ ... ticore.cpp
the function
boolean CMultiCoreSupport::LocalInterruptHandler (void)

I may be wrong talk to him about the general setup and especially his use of the tables.
If "rst" is around hopefully he will comment because he could be a big help to you.

btauro
Posts: 30
Joined: Fri Jan 12, 2018 3:11 am

Re: Difference between Interrupts in x86 and Exceptions in Arm

Thu Jan 18, 2018 4:52 am

Thank you so much for helping me out.
i am very grateful to this forum get to learn a lot

Thanks

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