leo96
Posts: 3
Joined: Mon Aug 14, 2017 10:42 pm

Interrupt relationship between ARM and BCM 2836

Mon Aug 14, 2017 11:00 pm

Hi everyone. I'm trying to build my own OS for hobby, but I'm having some doubts about how the ARM processor and the SoC handle interrupts. I know that on the ARM the interrupt vector has only one line for a generic IRQ and one for the FIQ, and that the BCM2836 has an another vector for its interrupt. I don't get how they are related in order to write an handler for them. What I suppose is that the BCM interrupt is connected to the IRQ and FIQ line of the ARM, so if it's true I have to poll every peripheral interrupt register in order to find out who raises the interrupt? If instead this is not how all works, can anyone explain it to me please?

I have also another question: I think that if I use an USB keyboard with my Raspberry anytime I press a key the OS is noticed of that by an interrupt, but neither in the BCM2835 or in the BCM2836 manual I was able to find any interrupt line for the USB. They're telling me that I have to poll all the time the registers for getting a key?

Leonardo

dwelch67
Posts: 835
Joined: Sat May 26, 2012 5:32 pm

Re: Interrupt relationship between ARM and BCM 2836

Tue Aug 15, 2017 3:00 am

There is an interrupt controller on the broadcom side of the arm core, you dont have to poll the interrupts you read a status register and it shows you the asserted interrupt(s).

I dont know the usb interface but there are a number here that do, you can do an experiment and generate a usb interrupt then check the status register and one of the undocumented interrupt lines may light up...Best to look around this forum or one of the folks that have implemented usb drivers in bare metal.

leo96
Posts: 3
Joined: Mon Aug 14, 2017 10:42 pm

Re: Interrupt relationship between ARM and BCM 2836

Tue Aug 15, 2017 5:57 am

Thank you dwelch67 for your quick response. I'm still not undestanding a thing: the ARM processor so has knowledge about the peripherals interrupts, jumping straight to the handler, or it's based on the use of the IRQ and FIQ lines?

inaciose
Posts: 15
Joined: Thu Aug 24, 2017 3:34 pm

Re: Interrupt relationship between ARM and BCM 2836

Thu Aug 24, 2017 5:18 pm

When the interrupt is raised, for instance by a configured timer. The CPU change to Irq mode and process the code in irq handler function, you setup on your irq vector.

dwelch67
Posts: 835
Joined: Sat May 26, 2012 5:32 pm

Re: Interrupt relationship between ARM and BCM 2836

Thu Aug 24, 2017 8:23 pm

the broadcom part of the chip has an interrupt controller/manage, the many possible interrupts from the peripherals feed directly into that. In that interrupt controller you can enable one or more of those to be tied to the irq or fiq lines. So if any one of them you have enabled fires it will then hit the single irq line on the arm core and if you have interrupts enabled in the arm core (cpsr) then the exception will get executed.

the newer cores are a little more complicated and may have more than one irq line on the edge of the core, I am not sure, but they are still using the broadcom interrupt manager and have disabled the arm core NVIC.

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