deater
Posts: 14
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Location: 45N

pi3 PMU interrupt settings

Mon Aug 14, 2017 4:04 pm

Hello

I'm trying to get the hardware performance counters (PMU) going on 64-bit-pi3 with upstream Linux, which involves having the proper PMU Interrupt settings in the device-tree file. Is there documentation available on what these settings should be for pi3?

For example, on a similar architecture they have something like this:
arm-pmu {
compatible = "arm,cortex-a53-pmu";
interrupts = <9>, // IRQ_TYPE_LEVEL_HIGH
<10>, // IRQ_TYPE_LEVEL_HIGH
<11>, // IRQ_TYPE_LEVEL_HIGH
<12>; // IRQ_TYPE_LEVEL_HIGH
interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
};

LdB
Posts: 562
Joined: Wed Dec 07, 2016 2:29 pm

Re: pi3 PMU interrupt settings

Mon Aug 14, 2017 4:39 pm

Try the question in the right forum, I am guessing device tree or raspbian. You are in the baremetal forum what is linux :-)

deater
Posts: 14
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Location: 45N

Re: pi3 PMU interrupt settings

Mon Aug 14, 2017 4:50 pm

Fine, let me rephrase it in a way that's also true. I have my own baremetal OS I am writing and I am trying to get the PMU to work. Does anyone know the proper PMU interrupt number/types for the Pi3?

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Ultibo
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Joined: Wed Sep 30, 2015 10:29 am
Location: Australia

Re: pi3 PMU interrupt settings

Mon Aug 14, 2017 11:46 pm

deater wrote:
Mon Aug 14, 2017 4:04 pm
Is there documentation available on what these settings should be for pi3?
Hi,

The PMU interrupts appear in the local peripherals block on the Pi2 and Pi3, section 4.10 of the QA7 document shows it as bit 9 of the core Interrupt source registers.

There is one register for each core but the layout is the same for all of them, in bare metal you'll need to invent some kind of numbering scheme that allows you to refer to them. I don't know exactly what Linux does but in our case we map them onto the end of the main set of interrupts (the GPU interrupts as they are called) and the PMU ends up as IRQ 105, you can arrive at whatever arrangement you need.
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https://ultibo.org

deater
Posts: 14
Joined: Fri Mar 11, 2016 3:58 pm
Location: 45N

Re: pi3 PMU interrupt settings

Tue Aug 15, 2017 8:06 pm

Ultibo wrote:
Mon Aug 14, 2017 11:46 pm
The PMU interrupts appear in the local peripherals block on the Pi2 and Pi3, section 4.10 of the QA7 document shows it as bit 9 of the core Interrupt source registers.

There is one register for each core but the layout is the same for all of them, in bare metal you'll need to invent some kind of numbering scheme that allows you to refer to them. I don't know exactly what Linux does but in our case we map them onto the end of the main set of interrupts (the GPU interrupts as they are called) and the PMU ends up as IRQ 105, you can arrive at whatever arrangement you need.
Thanks!

For what it's worth, on Linux the PMU interrupt gets assigned to IRQ9 which makes sense based on the document you posted.

colinh
Posts: 94
Joined: Tue Dec 03, 2013 11:59 pm
Location: Munich

Re: pi3 PMU interrupt settings

Wed Aug 16, 2017 12:14 am

deater wrote:
Mon Aug 14, 2017 4:50 pm
Fine, let me rephrase it in a way that's also true. I have my own baremetal OS I am writing and I am trying to get the PMU to work. Does anyone know the proper PMU interrupt number/types for the Pi3?
Ooh! Sneaky! I see what you did there. :D
For what it's worth, on Linux the PMU interrupt gets assigned to IRQ9 which makes sense based on the document you posted.
Nope! you said "Linux" again! :evil:

deater
Posts: 14
Joined: Fri Mar 11, 2016 3:58 pm
Location: 45N

Re: pi3 PMU interrupt settings

Fri Aug 18, 2017 9:18 pm

colinh wrote:
Wed Aug 16, 2017 12:14 am
deater wrote:
Mon Aug 14, 2017 4:50 pm
Fine, let me rephrase it in a way that's also true. I have my own baremetal OS I am writing and I am trying to get the PMU to work. Does anyone know the proper PMU interrupt number/types for the Pi3?
Ooh! Sneaky! I see what you did there. :D
I do have such an OS, and it does have performance monitor support though I haven't finished porting it to Pi3 yet, hence the question. I was working on getting the support upstream into Linux first to make sure it works before adding the same to my OS.

http://www.deater.net/weave/vmwprod/vmwos/

I was asking here because the upstream Linux pi maintainer thought this would be the best place to ask.

Anyway he also wanted me to ask if anyone knew if the PMU interrupts are EDGE or LEVEL, as that wasn't in the document linked to earlier.

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