Thanks!Ultibo wrote: ↑Mon Aug 14, 2017 11:46 pmThe PMU interrupts appear in the local peripherals block on the Pi2 and Pi3, section 4.10 of the QA7 document shows it as bit 9 of the core Interrupt source registers.
There is one register for each core but the layout is the same for all of them, in bare metal you'll need to invent some kind of numbering scheme that allows you to refer to them. I don't know exactly what Linux does but in our case we map them onto the end of the main set of interrupts (the GPU interrupts as they are called) and the PMU ends up as IRQ 105, you can arrive at whatever arrangement you need.
Ooh! Sneaky! I see what you did there.
Nope! you said "Linux" again!For what it's worth, on Linux the PMU interrupt gets assigned to IRQ9 which makes sense based on the document you posted.
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