Okay this is about security what they are trying to do is setup what on an Intel processor they call rings of security. So the O/S system runs at the highest privilege, Device drivers then App run at a lower and finally Users run at the lowest. So to switch security levels they want to be able to monitor it which is why you can't just flick a register.Makogan wrote:First, how is that subroutine returning? Like if I look at your subroutine, the last statement is mov r0, #1
This naming in ARM security I also find weird having come from Intel. It's actually covered reasonably well in wikipedia under protection ringMakogan wrote: Second, why is it that being in Hyp mode prevents you from going into lower priviledged modes? that makes no sense in my head...
So that is why the Pi starts in PL2 (HYP_MODE) because it should start in highest security. Originally in history it didn't we got the ARM in SVC_MODE but they changed the bootloader.The ARM v7 architecture implements three privilege levels: application, operating system, and hypervisor. Unusually, level 0 (PL0) is the least-privileged level, while level 2 (PL2) is the most-privileged (hypervisor) level
eret is a special returnMakogan wrote: How does it return to it's calling code without an explicit branch instruction?
You obviously can't load ELR_hyp is you aren't in HYP_MODE and now go look at the code againWhen executed in Hyp mode, ERET loads the PC from ELR_hyp and loads the CPSR from SPSR_hyp
You didn't waste my time. I am working on a commercial product using the Pi3 and it is just part of time I have dedicated to learning the Pi3 anyhow.Makogan wrote: On any case thank you for helping me, I know it was my fault and that I wasted your time, I am sorry.
Martin Weidmann,ARM wrote:Take the example of a 64-bit OS running a 32-bit app. You are initially in EL1 as AArch64, running kernel code. The OS loads the context for the 32-bit app, and performs an exception return down to EL0. Switching to AArch32. On the next exception (e.g. scheduler tick, or system call) you transition back to EL1/AArch64.
Code: Select all
.globl cbar cbar: //mrs x0,cbar_el1 mrs x0,s3_1_c15_c3_0 ret
David,dwelch67 wrote: but perhaps the GIC is it...There is supposed to be a timer as well...
dwelch67 wrote:Currently playing with the timer, appears so far to be 250Mhz/256 like the system timer
David,dwelch67 wrote:The SYSTIMERCLO timer and the cntpct_el0 timer are fairly close, but there is about a 2 count or so per second difference between them.
That seems to fit with all of the other information available.dwelch67 wrote:ID_PFR1_EL1 shows that GICDISABLE is high, disabled. as you already knew or suspected...