ldrex/strex are supposed to be for multi core sharing, not for other uses, although they have been.
The arm logic supports them correctly (unless you find an errata), but the chip vendor logic may or may not, I checked the pi1 and it did work, and per the arm docs for multicore the chip vendor needs to support it.
It is tricky to get the transaction(s) into the chip vendors code anyway, if you have the data cache on which ideally means you have the mmu on then are pretty much in ARM's logic domain and they should just work.
Clearly you have talked through the other details with other folks here, and there are more issues than just whose logic is seeing these transaction pairs. Since I have been personally burned by these instructions and learned by chance from at least another who got burned, I like to share this knowledge. Some arm docs tell one story, others tell another, taken as a whole you have to be careful when using them, specifically uniprocessor as the arm docs say that the chip vendor doesnt have to support exclusive access on a uniprocesor and can return OKAY. Assuming you are on a pi2 or pi3 then ARM does say/imply you should support exclusive access and return the appropriate response.