timanu90
Posts: 52
Joined: Sat Dec 24, 2016 11:54 am

ldrex/strex

Wed Jan 04, 2017 8:13 pm

Hi guys.

I am trying to use ldrex/strex for spinlock implementation.

I read in this forum that I need both caches activated to work. (I have)

But don't work, so i went read Instruction Set Attributes Register 3 and this register returned 0x01240000 value. Wich means this instructions are not supported.

This seems odd because this are key instructions for syncronization and some folks said they used them.

Can any one corfirm this or tell me if I need more than the caches activated?

Tiago

rst
Posts: 279
Joined: Sat Apr 20, 2013 6:42 pm
Location: Germany

Re: ldrex/strex

Wed Jan 04, 2017 9:28 pm

Are you sure, you have read the Instruction Set Attributes Register 3 (ID_ISAR3)? For me it reports 0x11112131 on the RPi 2 (first revision) and 0x01112131 on the RPi 3 which means these instructions are implemented, which is definitely the case.

timanu90
Posts: 52
Joined: Sat Dec 24, 2016 11:54 am

Re: ldrex/strex

Wed Jan 04, 2017 9:48 pm

Ya you right I messed up the read register. Bu still I have this annoying data aborts and I don't know why.

You already worked with this instructions?

rst
Posts: 279
Joined: Sat Apr 20, 2013 6:42 pm
Location: Germany

Re: ldrex/strex

Thu Jan 05, 2017 7:38 am

Yes, I implemented spin-locks with them. Have a look at section D7.3 of the ARMv7-A Architecture Reference Manual. The code there is simple and works well.

Be sure to place the lock variable in a memory region which has the S-bit (shareable) set in the translation table.

timanu90
Posts: 52
Joined: Sat Dec 24, 2016 11:54 am

Re: ldrex/strex

Thu Jan 05, 2017 9:16 am

Thank you very much for your indications. My code is very similar to that one in section D7.3. But you said I need to make the memory shareable in page table, that means I need MMU enabled. I will configure the MMU and try again.

Tiago

rst
Posts: 279
Joined: Sat Apr 20, 2013 6:42 pm
Location: Germany

Re: ldrex/strex

Thu Jan 05, 2017 10:16 am

Yep, the ldrex/strex instructions only work with MMU enabled. This is also the case for the data cache. Because you wrote, you have it on, I thought you are already using the MMU.

The reason for this behaviour is, that ldrex/strex only work with "Normal memory". But when the MMU is disabled, the memory is "Strongly-Ordered". You really need the MMU.

timanu90
Posts: 52
Joined: Sat Dec 24, 2016 11:54 am

Re: ldrex/strex

Thu Jan 05, 2017 10:47 pm

Hello again. I managed to turn on MMU with minimum configuration. Things are working now but with a thing that annoy me. I have to clean data cache before use my spin_lock or spin_unlock functions.
It happened to someone something similar?

Btw the difference in speed with dcache on is amazing. LED blink so much faster xD.

Tiago

rst
Posts: 279
Joined: Sat Apr 20, 2013 6:42 pm
Location: Germany

Re: ldrex/strex

Fri Jan 06, 2017 9:56 am

timanu90 wrote:I have to clean data cache before use my spin_lock or spin_unlock functions.
That's odd. Does your kernel7.img start at 0x8000 as normal, or do you use the kernel_old=1 option in config.txt? I'm asking because in the first case an ARM stub is used, which does an additional initialisation to enable SMP operation. I the second case you have to do this on your own.

timanu90
Posts: 52
Joined: Sat Dec 24, 2016 11:54 am

Re: ldrex/strex

Fri Jan 06, 2017 10:02 am

I didn't modify config.txt. I use dwelch67 bootloader07 to load my kernel nothing more.
But maybe is my MMU configuration.
When i get home i will try test other memory configurations. I read 27troadster latest post on viewtopic.php?f=72&t=122181, where he explains the diferent policies for caching memory, maybe i have a similar problem.

Tiago

timanu90
Posts: 52
Joined: Sat Dec 24, 2016 11:54 am

Re: ldrex/strex

Fri Jan 06, 2017 7:43 pm

Well just to let you guys know, I already removed the chache clean. I had my secions mapped on MMU as cacheable, bufferable, shareable and tex bit active. I left only cacheable and shareable and it worked.

Now is time to read arm architeture again to refresh the memory types again.

rst really thank you for your help.

Tiago

rst
Posts: 279
Joined: Sat Apr 20, 2013 6:42 pm
Location: Germany

Re: ldrex/strex

Sat Jan 07, 2017 12:28 pm

You are welcome.

Rene

dwelch67
Posts: 825
Joined: Sat May 26, 2012 5:32 pm

Re: ldrex/strex

Tue Jan 10, 2017 3:34 pm

ldrex/strex are supposed to be for multi core sharing, not for other uses, although they have been.

The arm logic supports them correctly (unless you find an errata), but the chip vendor logic may or may not, I checked the pi1 and it did work, and per the arm docs for multicore the chip vendor needs to support it.

It is tricky to get the transaction(s) into the chip vendors code anyway, if you have the data cache on which ideally means you have the mmu on then are pretty much in ARM's logic domain and they should just work.

Clearly you have talked through the other details with other folks here, and there are more issues than just whose logic is seeing these transaction pairs. Since I have been personally burned by these instructions and learned by chance from at least another who got burned, I like to share this knowledge. Some arm docs tell one story, others tell another, taken as a whole you have to be careful when using them, specifically uniprocessor as the arm docs say that the chip vendor doesnt have to support exclusive access on a uniprocesor and can return OKAY. Assuming you are on a pi2 or pi3 then ARM does say/imply you should support exclusive access and return the appropriate response.

franksai
Posts: 6
Joined: Thu Jun 08, 2017 11:07 am

Re: ldrex/strex

Thu Aug 24, 2017 7:12 am

How did you make your ldrex works?

I want to use it at PI2.
What i have done is set memory attribute as shareable and normal, and enable 4 core MMU.
But ldrex still can't work

Should I try to enable cache?
Or something else?

timanu90
Posts: 52
Joined: Sat Dec 24, 2016 11:54 am

Re: ldrex/strex

Tue Aug 29, 2017 1:51 pm

Yes you need data cache enabled on the RPI2.

dwelch67
Posts: 825
Joined: Sat May 26, 2012 5:32 pm

Re: ldrex/strex

Tue Aug 29, 2017 9:12 pm

historically and per the arm requirements you dont need any caches on but you can just try it.

franksai
Posts: 6
Joined: Thu Jun 08, 2017 11:07 am

Re: ldrex/strex

Wed Aug 30, 2017 1:38 am

I have enabled I_cache and D_cache, but the system still fail.
Even if I just insert the following code to boot code

Code: Select all

ldrex r0,[r0]

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