According to the linux headers (see below), interrupts 12 to 15 are multicore sync 0-3. These interrupts are completely undocumented, can anyone tell me what they do?
https://github.com/raspberrypi/linux/bl ... platform.h
They seem to be related to the "local" interrupts (i.e. the 20 interrupts local to the core, not the 72 global interrupts that broadcomm calls gpu interrupts). But I can't find any other mentions of them in linux or anywhere else
Re: what are the multicore sync interrupts on pi-2?
Good question, I would kind of be interested in the answer myself.
With my multi core play I have not been thinking about using inturupts to sync the CPU's in any way, just using traditional async multi core methods, with traditional locks for shared data/code.
With my multi core play I have not been thinking about using inturupts to sync the CPU's in any way, just using traditional async multi core methods, with traditional locks for shared data/code.
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Re: what are the multicore sync interrupts on pi-2?
Are you referring to Inter-Processor Interrupt <https://en.wikipedia.org/wiki/Inter-processor_interrupt>?
Re: what are the multicore sync interrupts on pi-2?
I'm still studying low-level stuff. But I think it may be useful when a core wants other cores to invalidate their cache.DavidS wrote:Good question, I would kind of be interested in the answer myself.
With my multi core play I have not been thinking about using inturupts to sync the CPU's in any way, just using traditional async multi core methods, with traditional locks for shared data/code.
Re: what are the multicore sync interrupts on pi-2?
Maybe, or maybe not.xihan94 wrote:I'm still studying low-level stuff. But I think it may be useful when a core wants other cores to invalidate their cache.DavidS wrote:Good question, I would kind of be interested in the answer myself.
With my multi core play I have not been thinking about using inturupts to sync the CPU's in any way, just using traditional async multi core methods, with traditional locks for shared data/code.
Generaly shared memory is write through, unless the task performs better with cached mem for the small amount shared, despite the overhead of a cache flush.
RPi = The best ARM based RISC OS computer around
More than 95% of posts made from RISC OS on RPi 1B/1B+ computers. Most of the rest from RISC OS on RPi 2B/3B/3B+ computers
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Re: what are the multicore sync interrupts on pi-2?
From the platform.h file these appear to be in the GPU interrupts and not in the ARM local interrupts so they are likely for the multiple cores in the GPU itself.Kapp3t wrote:interrupts 12 to 15 are multicore sync 0-3. These interrupts are completely undocumented, can anyone tell me what they do?
Code: Select all
#define INTERRUPT_MULTICORESYNC0 (ARM_IRQ1_BASE + 12)
#define INTERRUPT_MULTICORESYNC1 (ARM_IRQ1_BASE + 13)
#define INTERRUPT_MULTICORESYNC2 (ARM_IRQ1_BASE + 14)
#define INTERRUPT_MULTICORESYNC3 (ARM_IRQ1_BASE + 15)
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