Help with PCM block

[valtonia]

Hi All,

I'm trying to get the PCM block working, trying a simple test (in polling mode) to just get some noise out of the Rpi and it's sort of half working, but behaving in strange way.

First, the sync bit in the cs_a register - the doc says write 1 to this and 2 clocks later it will read back as 1. Doesn't seem to be working for me. I write 1, the value reads back as 0 forever.

Second, by following the bcm2835 doc I'm trying the following sequence:

enable pcm block:
set cs_a.en = 1

clear any errors/reset fifo's:
set cs_a.txclr = 1
set cs_a.txerr = 1
set cs_a.rxclr = 1
set cs_a.rxerr = 1

set up the channels:
txc_a.ch1en = 1
txc_a.ch1pos = 0
txc_a.ch1wid = 8
txc_a.ch1wex = 0
(ch2 disabled for this test)

set up the mode: (this is the part I've probably got wrong)
mode_a.clk_dis = 0
mode_a.pdmn = 0
mode_a.pdme = 0
mode_a.frxp = 0
mode_a.ftxp = 0
mode_a.clkm = 0
mode_a.clki = 0
mode_a.fsm = 0
mode_a.fsi = 0
mode_a.flen = 1
mode_a.fslen = 1

Finally, I write to fifo_a until cs_a.txd = 0 and then I write cs_a.txon = 1. (I've also tried setting cs_a.stby = 1 but no change).

At this point I expect the fifo to start emptying and the txw, txe and, txd bits to change, but nothing happens at all.

I know it's hard to diagnose from this description without seeing my code or anything, but can anyone think of anything obvious I'm missing?

Cheers,
A.

[malte30]

Hi,

i've a very similiar problem...
i write to fifo_a until cs_a.txd goes up high and the fifo is full (cs_a.txon = 0) but this never happens!
It seems that the writes to fifo_a register dont get bto the peripheral...

@valtonia: Did you found a solution??

Regards
Malte

[jdb]

You need a clock source.

CM_PCMCTL / CM_PCMDIV are the registers you need to poke:
https://github.com/torvalds/linux/blob/ ... -bcm2835.c

[malte30]

Thanks for your reply

I already had the clock source... made a stupid mistake and overlooked that i did not enable the peripheral in cs_a.en=1.

Regards
Malte