vsiles wrote:Here are the details:
- My MMU maps the memory as section, with the S bit set in the mappings
I'm pretty sure that having the S-bit set (designating the section of memory as "shared") will turn off level 1 data caching. From ARM1176 tech manual, pg 6-21, paragraph titled"shared normal memory" is the statement: "The processor does not cache shareable locations at level one."
So even if the C bit is set, and D-Cache is enabled in CP15, if the S-bit is set it will override these and data caching will not occur. I do not know how the Pi deals with cache coherency for shared sections of memory in Level 2 cache.