I'm trying to implement a spinlock on Pi 1. Spinlocks are basically just interrupt disables in uniprocessor systems, but doesn't it need an instruction barrier as well?
I am using the Linux kernel as reference, and there, the sequence I can see looks like this (for spin_lock_irqsave):
* Read IRQ state
* compiler optimisation barrier
I'm wondering why there is no ISB instruction here? Is it implied in cpsid? Or is there some guarantee that the cpsid instruction takes effect before any instruction that follows it in the pipeline?