Posts: 76
Joined: Sun Apr 15, 2012 2:23 pm

Spinlocks and barriers

Wed Jul 29, 2015 11:04 pm

I'm trying to implement a spinlock on Pi 1. Spinlocks are basically just interrupt disables in uniprocessor systems, but doesn't it need an instruction barrier as well?

I am using the Linux kernel as reference, and there, the sequence I can see looks like this (for spin_lock_irqsave):

* Read IRQ state
* cpsid
* compiler optimisation barrier

I'm wondering why there is no ISB instruction here? Is it implied in cpsid? Or is there some guarantee that the cpsid instruction takes effect before any instruction that follows it in the pipeline?

Raspberry Pi Engineer & Forum Moderator
Raspberry Pi Engineer & Forum Moderator
Posts: 2240
Joined: Thu Jul 11, 2013 2:37 pm

Re: Spinlocks and barriers

Mon Aug 03, 2015 10:59 am

The ISB flushes the execution pipeline and ensures that all instruction memory accesses are serialised after the ISB. It's not necessary in the case of disabling/enabling interrupts because when you execute a CPSI(D, E), you can assume that the processor exception handling state takes effect before the execution of the next instruction.
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