Did a little research and found this:
http://infocenter.arm.com/help/index.js ... a8404.html
I'm probably just reading this wrong, but it seems to imply I need the SCU for atomics to work in my case. I found the SCU control and configuration register offsets from PERIPHBASE, and then tried to get the PERIPHBASE address with
Code: Select all
mrc p15, 4, r1, c15, c0, 0
So, my questions are:
0) am I really on the right track, or should the SCU not be needed?
1) PERIPHBASE is the reset value. Should it be zero and do I need to set it somewhere else?
2) is there anything else I may have missed in getting ldrex and strex to work across multiple cores
The other possibility is that I messed up something silly in my setup somewhere and atomic should work fine from normal shared cached regions without the SCU