turboscrew
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Good asm-learning books?

Tue Mar 31, 2015 9:59 pm

I wonder if anyone has come across a good book on ARM assembly programming that goes beyond the user level? I found myself wondering about SW exceptions - ways of triggering them, ways to handle them and ways from returning. I got the impression (from the ARM manuals) that BKPT doesn't have vectors, but it causes a state (or was it mode or something else - I'm confused) change to debug (whatever that is) where the PC and SP are banked? Then there is the (secure) monitor state (or was it mode?) and it works basically the same way, except some bits in some registers needs to be set to have rights to get there?

I could use a book that clears those things up...
Reading the ARM manuals is like reading law text for an ARM-noobie.

The problem is that the bookshops don't have those books any more. They have to be ordered from the net, and one can not look into them to find out if a book matches one's needs or not.
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turboscrew
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Re: Good asm-learning books?

Wed Apr 01, 2015 11:13 am

I came to realize that a good explanation of the instruction sets would be great too.
Does ARM have PC-relative load with auto-increment? Or how do you get to manipulate
32-bit values? I understand that '=value' pseudo puts the value into a constant pool nearby, but what,
if there are no 'near-enough-by' place? I haven't found any 16-bit immediate loading instructions either (to load high and low parts separately).

The tutorials I've found this far haven't shown any tricks, but restricted themselves to 8-bit values (and begin by 10-page explanation of what register is), and the ARM documents usually show instruction set coding, where the info for one complete instruction is scattered around the document.

An instruction list with restrictions would be excellent.
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rpdom
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Re: Good asm-learning books?

Wed Apr 01, 2015 12:00 pm

Most of the books and examples will tell you what the instructions do. Best thing is to forget pretty much everything you have learned about other processors.

For loading values you have the "mov Rd, #n [,shift]" method with n being an 8 bit value and shift being an option even number of bits to shift the value in either direction before loading.

You also have the indirect method with ldr, which uses a register holding the address of the source (plus an offset, which can also be shifted). You can use any register for the source, including R15 (PC). Using R15 is common for local values.

The easiest way of loading a 16 bit value (well, it's really a 32 bit value, just with two bytes of the value being zero), is to use two instructions. Usually a "mov Rd, #n" followed by an "add Rd, Rd, #n, lsl #8" or "orr Rd, Rd, #n, lsl #8". In most assemblers you can just put the actual value of the high 8 bytes, as in 0x1200, and it will turn that into 0x12, lsl #8 for you.

Some "16 bit" values, like 0x0ff0 can be loaded with just one mov instruction due to the shift. "mov r0, #0x0ff0" is translated to "mov r0, #0xff, lsl 4".

turboscrew
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Re: Good asm-learning books?

Wed Apr 01, 2015 1:51 pm

rpdom wrote:Most of the books and examples will tell you what the instructions do.
That's the problem. I pretty much know what they do, but what I don't know is which 'variations' I have available (mainly addressing modes).
Best thing is to forget pretty much everything you have learned about other processors.
I've come to see what you mean, although not so many miles away from PPC.
(link register, rlwinm & friends, ...)
And VAX11 instruction set in not very conventional either... :lol:
(evaluate polynomial, edit character string, ...)
For loading values you have the "mov Rd, #n [,shift]" method with n being an 8 bit value and shift being an option even number of bits to shift the value in either direction before loading.

You also have the indirect method with ldr, which uses a register holding the address of the source (plus an offset, which can also be shifted). You can use any register for the source, including R15 (PC). Using R15 is common for local values.
If there was auto-increment, there would have been immediate - something like
LDR R0, [PC++] - like in some architectures - the '++' skips the 'immediate'.
The easiest way of loading a 16 bit value (well, it's really a 32 bit value, just with two bytes of the value being zero), is to use two instructions. Usually a "mov Rd, #n" followed by an "add Rd, Rd, #n, lsl #8" or "orr Rd, Rd, #n, lsl #8". In most assemblers you can just put the actual value of the high 8 bytes, as in 0x1200, and it will turn that into 0x12, lsl #8 for you.

Some "16 bit" values, like 0x0ff0 can be loaded with just one mov instruction due to the shift. "mov r0, #0x0ff0" is translated to "mov r0, #0xff, lsl 4".
[/quote]
Pretty tough with 32-bit masks: I should mask bit 24 and 13 off: r0 = r0 & ~(0x0801<<13).
What kind of tricks do people 'cultivate' in situations like this?
Block of constants? Building the value using 4 bytes? Masking bits one-by-one (or in 8-bit groups)?
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Re: Good asm-learning books?

Wed Apr 01, 2015 2:49 pm

turboscrew wrote:Pretty tough with 32-bit masks: I should mask bit 24 and 13 off: r0 = r0 & ~(0x0801<<13).
What kind of tricks do people 'cultivate' in situations like this?
Block of constants? Building the value using 4 bytes? Masking bits one-by-one (or in 8-bit groups)?
All sorts of tricks. For that situation I'd probably use two instructions:
orr r0, #0x0800
orr r0, #0x01
letting the assembler work out the shift/rotate on the first one for me (it would change it to something like orr r0, r0, #8, lsl #8). Alternatively you could have the mask stored in another register.

There are lots of little tricks you can do with the ARM features like the barrel shifter and pretty much every instruction being conditional. Multiply by 5 in one simple instruction (the original ARM core didn't have a MUL instruction and when one was introduced it took more clock cycles than other instructions, although that's probably unimportant with the current versions): add r0, r0, r0, lsl #2 (r0 = r0 + r0 <<2)

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Re: Good asm-learning books?

Wed Apr 01, 2015 2:59 pm

Those things I'd like to see in a book/tutorial/...:
orr r0, #0x0800
and
letting the assembler work out the shift/rotate on the first one for me
It's just that 'as' can't document the instruction set of all the ISAs it supports, and ARM thinks it's up to the assembler makers (well those ARE assembler-features).

Is it so, that there is no instruction with immediate data bigger than 8 bits?
Immediate address offsets can be bigger?

[edit}
Forgot: so the masking off is something like:

Code: Select all

mvn.w r0, #0
bic.w r0, #1, lsl 24
bic.w r0, #2, lsl 12
mrc p15, 0, r1, 1, 0, 0
and.w r1, r0
mcr p15, 0, r1, 1, 0, 0
(Should the '.w' be there?)
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tufty
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Re: Good asm-learning books?

Wed Apr 01, 2015 5:57 pm

There is auto-increment.

Code: Select all

;; Load Rt with the contents of memory pointed to by Rn (plus or minus 12 bit value imm), update Rn
LDR<c> <Rt>,[<Rn>,#±<imm>]!
;; Load Rt with contents of memory pointed to by Rn, update Rt by adding / subtracting 12 bit value imm
LDR<c> <Rt>, [<Rn], #±<imm>
Those are the simple ones, and give you ±4096 bytes of offset. Want something more?

Code: Select all

;; Load Rt with contents of memory pointed to by Rn plus or minus optionally shifted Rm, update Rn
LDR<c> <Rt>,[<Rn>,±<Rm>{,<shift>}]!
;; Load Rt with contents of memory pointed to by Rn, update Rn by adding / subtracting optionally shifted Rm
LDR<c> <Rt>,[<Rn>],±<Rm>{,<shift>}
Allowable values vary dependent on if you're using Thumb or ARM.
Is it so, that there is no instruction with immediate data bigger than 8 bits?
No, it is not so. ARM immediates are generally "modified 12 bit" values, which means that the immediate data (or its complement) must fit in 8 bits, shifted by a multiple of 2. ARMv7 and Thumb2 have some 16 bit loads.

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Re: Good asm-learning books?

Wed Apr 01, 2015 6:14 pm

To visualise what's do-able with 12 bit immediates, you must understand that the set (or unset, in the case of complemented values) bits in the required value must all be at least in one contiguous 8 bit span. In other words, it must be possible to rotate the value to give a value <= 0xff

With that in mind, imagine trying to encode 0xff (the maximum 8 bit number) rotated left by varying amounts
0x000000ff - OK
0x000001fe - Not OK
0x000003fc - OK
… and so on up to 0x8000007f. Even rotates of 8 bits are OK, but "odd" rotates translate to an even rotate of 9 bits - no good. This is going to hold for any number where the top and bottom bits of the 8 bit "populated" area are set, i.e. 0b1xxxxxx1 where we don't care about x. Anything which rotates to an 8-bit value with the top bit set is restricted to where it can be rotated back to.

However, any number which has set bits spanning less than 7 bits can be encoded in any position.

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Re: Good asm-learning books?

Wed Apr 01, 2015 7:33 pm

tufty wrote:There is auto-increment.

Code: Select all

;; Load Rt with the contents of memory pointed to by Rn (plus or minus 12 bit value imm), update Rn
LDR<c> <Rt>,[<Rn>,#±<imm>]!
;; Load Rt with contents of memory pointed to by Rn, update Rt by adding / subtracting 12 bit value imm
LDR<c> <Rt>, [<Rn], #±<imm>
Those are the simple ones, and give you ±4096 bytes of offset. Want something more?

Code: Select all

;; Load Rt with contents of memory pointed to by Rn plus or minus optionally shifted Rm, update Rn
LDR<c> <Rt>,[<Rn>,±<Rm>{,<shift>}]!
;; Load Rt with contents of memory pointed to by Rn, update Rn by adding / subtracting optionally shifted Rm
LDR<c> <Rt>,[<Rn>],±<Rm>{,<shift>}
Allowable values vary dependent on if you're using Thumb or ARM.
With jumps it should work without autoincrement, since the execution doesn't continue after that, but in the loads it doesn't work , since the autoincrement is pre-increment. Only post-increment would work. Otherwise the next fetched 'instruction' would be the 'immediate data'.

LDR PC, [PC] @ if the PC points to the next 'instruction' when this instruction is executed.
.word 0xFFFFFFF0
Of course prefetch may mess that up irreparably, or make negative offset necessary.
I'm not deep enough in 'ARMonomics' to know...
[edit] Or then not. It should be already fetched. It could have been undefined instruction as well. [/edit]
In PDP-11 (and I think in 680x0 too) there were no true full immediate, but the same thing was achieved:
MOV R0, [R7++] ; I think R7 was PC on PDP-11, but it was decades ago...
.word 0xFFFF ; PDP-11 was 16-bit machine

Anyway, 12-bit offset make life a h***uvalot easier.
Is it so, that there is no instruction with immediate data bigger than 8 bits?
No, it is not so. ARM immediates are generally "modified 12 bit" values, which means that the immediate data (or its complement) must fit in 8 bits, shifted by a multiple of 2. ARMv7 and Thumb2 have some 16 bit loads.
Sorry, I meant more like 8 bits 'raw' immediate (before shifting).
Last edited by turboscrew on Wed Apr 01, 2015 7:47 pm, edited 2 times in total.
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turboscrew
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Re: Good asm-learning books?

Wed Apr 01, 2015 7:41 pm

tufty wrote:To visualise what's do-able with 12 bit immediates, you must understand that the set (or unset, in the case of complemented values) bits in the required value must all be at least in one contiguous 8 bit span. In other words, it must be possible to rotate the value to give a value <= 0xff

With that in mind, imagine trying to encode 0xff (the maximum 8 bit number) rotated left by varying amounts
0x000000ff - OK
0x000001fe - Not OK
0x000003fc - OK
… and so on up to 0x8000007f. Even rotates of 8 bits are OK, but "odd" rotates translate to an even rotate of 9 bits - no good. This is going to hold for any number where the top and bottom bits of the 8 bit "populated" area are set, i.e. 0b1xxxxxx1 where we don't care about x. Anything which rotates to an 8-bit value with the top bit set is restricted to where it can be rotated back to.

However, any number which has set bits spanning less than 7 bits can be encoded in any position.
I chose my words poorly - with 8-bit immediate I meant that 8-bit bit-span (runlength?).
(BTW, have to get a better look at lambda-pi as soon as I have time. I've always liked Lisp.)
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Re: Good asm-learning books?

Wed Apr 01, 2015 9:00 pm

I was searching for assembly conventions and I happened to hit
(ARM® Compiler Version 6.01armasm User Guide):
7.6 Load 32-bit values to a register using MOV32
Both A32 and T32 instruction sets include:
A MOV instruction that can load any value in the range 0x00000000 to 0x0000FFFF into a register.
A MOVT instruction that can load any value in the range 0x0000 to 0xFFFF into the most significant
half of a register, without altering the contents of the least significant half.
I checked that Cortex v7A has them.
Just, what the h*** are the different encodings? They seem to have restrictions, but are they assembler's headache, or does assembly programmer 'see' them?
<const> The immediate value to be placed in <Rd>. The range of values is 0-255 for encoding T1 and 0-65535
for encoding T3 or A2. See Modified immediate constants in Thumb instructions on page A6-232
or Modified immediate constants in ARM instructions on page A5-200 for the range of values for
encoding T2 or A1.
When both 32-bit encodings are available for an instruction, encoding T2 or A1 is preferred to
encoding T3 or A2 (if encoding T3 or A2 is required, use the MOVW syntax).
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Re: Good asm-learning books?

Wed Apr 01, 2015 9:36 pm

Still more findings:
Post-indexed addressing
The address obtained from the base register is used, unchanged, as the address for the memory
access. The offset value is applied to the address, and written back into the base register
The assembly language syntax for this mode is:
[<Rn>], <offset>
So
LDR R0, [PC], #4
.word 0xFFFFFFFF
should work?
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Re: Good asm-learning books?

Wed Apr 01, 2015 10:43 pm

turboscrew wrote:Still more findings:
Post-indexed addressing
The address obtained from the base register is used, unchanged, as the address for the memory
access. The offset value is applied to the address, and written back into the base register
The assembly language syntax for this mode is:
[<Rn>], <offset>
So
LDR R0, [PC], #4
.word 0xFFFFFFFF
should work?
Actually, that would probably need to be something like
LDR R0,[PC],#-4
as due to pipelining the PC points to the instruction being fetched, not the one being executed. The assemblers make allowances for this if you use labels.

As to the encodings, AIUI the T and A refer to Thumb and ARM mode, as the Thumb instruction set has a reduced capacity for values because the instructions only take up 16 bits each instead of 32, but take up less memory and (I think) may execute faster as one 32-bit fetch will load two instructions instead of one. The actual encodings are mostly the assembler's problem, but the programmer needs to be aware of what range of values is allowable for certain commands.

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Re: Good asm-learning books?

Thu Apr 02, 2015 12:04 am

but the programmer needs to be aware of what range of values is allowable for certain commands.
Thanks.
Actually, that would probably need to be something like
LDR R0,[PC],#-4
as due to pipelining the PC points to the instruction being fetched, not the one being executed.
I thought I took that into account?

Code: Select all

LDR R0, [PC], #4    @ when this executes, PC points to '.word' (probably already fetched)
.word 0xFFFFFFFF @ instead of executing this, PC is advanced to the next instruction (, #4)
The same logic that applies to, say:

Code: Select all

LDR PC, =somewhere_else
EOR PC, PC
That shouldn't cause reset?
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colinh
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Re: Good asm-learning books?

Thu Apr 02, 2015 12:51 am

The (free) book mentioned here is, IMHO, good.

http://www.raspberrypi.org/forums/viewt ... ll#p472980

tufty
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Re: Good asm-learning books?

Thu Apr 02, 2015 6:11 am

turboscrew wrote:
but the programmer needs to be aware of what range of values is allowable for certain commands.
Thanks.
The ARMv7AR-ARM (which covers the instruction sets used by both Pi models) describes all the encodings, by opcode, with any extra restrictions on availability.

So, for example, the MOVW / MOVT pair you were looking at are both only available for ARMv6T2 and ARMv7. Pi2 has ARMv7, which is fine, but the original Pi's ARM1176jzf-s doesn't have either.

Code: Select all

LDR R0, [PC], #4    @ when this executes, PC points to '.word' (probably already fetched)
.word 0xFFFFFFFF @ instead of executing this, PC is advanced to the next instruction (, #4)
In theory, yes, and it would be quite elegant, although slow. Unfortunately, I don't think you can use PC as the writeback register Rn in this case (ARMv7AR-ARM, page A8-121)

[edit] Aaargh, 8 bytes, as pointed out below.
Last edited by tufty on Thu Apr 02, 2015 6:35 am, edited 1 time in total.

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Re: Good asm-learning books?

Thu Apr 02, 2015 6:23 am

turboscrew wrote:
Actually, that would probably need to be something like
LDR R0,[PC],#-4
as due to pipelining the PC points to the instruction being fetched, not the one being executed.
I thought I took that into account?

Code: Select all

LDR R0, [PC], #4    @ when this executes, PC points to '.word' (probably already fetched)
.word 0xFFFFFFFF @ instead of executing this, PC is advanced to the next instruction (, #4)
The value of PC when any instruction is being executed is that instruction's address plus 8.
Here's some example code at a dummy address

Code: Select all

00008000 MOV R1, #0x8000 ; PC (R15) contains 00008008 when this is executed
00008004 ADD R1, #0x20 ; PC contains 0000800C
00008008 MOV R2, PC ; PC contains 00008010, so that value is put into R2.
00008010 MOV PC, R1 ; PC now changes to 00008020, the contents of R1
; The CPU will now fetch the instruction at 8020, then increment PC to 8024
; It will then decode the instruction from 8020, while fetching the next instruction from 8024, then increment PC to 8028
; Then it will execute the instruction from 8020, whilst decoding the instruction from 8024 and fetching the next instruction from 8028, then increment the again. The pipeline is now full and it carries on with normal execution.
This is why conditional instructions are used a lot as there is no need to refill the pipe in that case.

The modern ARMs actually have branch prediction and alternate pipelines which speed this process up, but the PC still points two instructions ahead of the instruction that is executing.
The same logic that applies to, say:

Code: Select all

LDR PC, =somewhere_else
EOR PC, PC
That shouldn't cause reset?
That is actually changing the value of PC, like the example above. The current contents of the pipe get dropped. You only need to be aware of the fact that the PC is 8 bytes ahead when using its value in an indirect or just reading it.

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Re: Good asm-learning books?

Thu Apr 02, 2015 6:44 am

colinh wrote:The (free) book mentioned here is, IMHO, good.

http://www.raspberrypi.org/forums/viewt ... ll#p472980
Thanks. I have seen it, but I thought it's helplessly outdated.
But now that in the thread you mentioned
...but almost all of it is still relevant.
I started reading.
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Re: Good asm-learning books?

Thu Apr 02, 2015 7:07 am

ARMv7AR-ARM?
Which document is that?
I have 'ARM-ARM',
DDI0406C_C_arm_architecture_reference_manual,
DDI0464F_cortex_a7_mpcore_r0p5_trm and
DEN0013D_cortex_a_series_PG
(And a bunch of others)
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tufty
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Re: Good asm-learning books?

Thu Apr 02, 2015 9:24 am

Mine's DDI 0406A "Arm Architecture Reference Manual ARM®v7-A and ARM®v7-R edition"

Your DDI 0406C is simply a later revision, so page numbers may not exactly match.

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Re: Good asm-learning books?

Thu Apr 02, 2015 6:26 pm

turboscrew wrote:
colinh wrote:The (free) book mentioned here is, IMHO, good.

http://www.raspberrypi.org/forums/viewt ... ll#p472980
Thanks. I have seen it, but I thought it's helplessly outdated.
But now that in the thread you mentioned
...but almost all of it is still relevant.
I started reading.
I hope you find it useful. From what you said you wanted, interrupt vector table, processor modes, what the instructions do, and how to use them efficiently for loops and subroutines etc, and the setting of flags and conditional execution etc..., for all that it's a very clear exposition.

It makes reading the ARM technical docs much easier when you're perfectly comfortable with the basics.

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Re: Good asm-learning books?

Thu Apr 02, 2015 10:57 pm

tufty wrote:Mine's DDI 0406A "Arm Architecture Reference Manual ARM®v7-A and ARM®v7-R edition"

Your DDI 0406C is simply a later revision, so page numbers may not exactly match.
In my document it says:
A8.8.62 LDR (immediate, Thumb)
...
Assembler syntax
LDR{<c>}{<q>} <Rt>, [<Rn> {, #+/-<imm>}] Offset: index==TRUE, wback==FALSE
LDR{<c>}{<q>} <Rt>, [<Rn>, #+/-<imm>]! Pre-indexed: index==TRUE, wback==TRUE
LDR{<c>}{<q>} <Rt>, [<Rn>], #+/-<imm> Post-indexed: index==FALSE, wback==TRUE
where:
<c>, <q> See Standard assembler syntax fields on page A8-287.
<Rt> The destination register. The SP can be used. The PC can be used, provided the instruction is either
outside an IT block or the last instruction of an IT block. If the PC is used, the instruction branches
to the address (data) loaded to the PC. In ARMv5T and above, this branch is an interworking branch,
see Pseudocode details of operations on ARM core registers on page A2-47.
<Rn> The base register. The SP can be used. For PC use see LDR (literal) on page A8-410.
and also
A8.8.63 LDR (immediate, ARM)
...
<Rn> The base register. The SP can be used. For PC use see LDR (literal) on page A8-410.
A8.8.64 LDR (literal)
...
<Rt> The destination register. The SP can be used. The PC can be used, provided the instruction is either
outside an IT block or the last instruction of an IT block. If the PC is used, the instruction branches
to the address (data) loaded to the PC. In ARMv5T and above, this branch is an interworking branch,
see Pseudocode details of operations on ARM core registers on page A2-47.
[edit]
Ah,
if wback && n == t then UNPREDICTABLE;
so jump doesn't work, but loading should.
And for Arm (not thumb):

Code: Select all

Encoding A1 ARMv4*, ARMv5T*, ARMv6*, ARMv7
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Re: Good asm-learning books?

Thu Apr 02, 2015 11:10 pm

colinh wrote: It makes reading the ARM technical docs much easier when you're perfectly comfortable with the basics.
I agree, totally.
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