I'm currently writing a simple OS for fun and educational purposes. The problem I'm currently trying to solve is updating the MMU page tables when a new task is loaded into the address space. Currently everything runs at EL1, identity mapped.
Arm® Architecture Reference Manual Armv8, for Armv8-A architecture profile
The AArch64 Virtual Memory System Architecture
D5.10 TLB maintenance requirements and the TLB maintenance instructions:
In D5.10.2 TLB maintenance instructions:A break-before-make sequence on changing from an old translation table entry to a new translation table entry
requires the following steps:
1. Replace the old translation table entry with an invalid entry, and execute a DSB instruction.
2. Invalidate the translation table entry with a broadcast TLB invalidation instruction, and execute a DSB
instruction to ensure the completion of that invalidation.
3. Write the new translation table entry, and execute a DSB instruction to ensure that the new entry is visible.
I must be in EL2 to perform TLB operations that affect EL1, correct? If so, is there another way to update page tables from EL1?An instruction that applies to the translation regime of an Exception level higher than
the Exception level at which the instruction is executed is UNDEFINED.
The other options are:
- Run tasks in EL0.
- Load all tasks into memory first then set page tables.
Thank you in advance for any assistance,