jahboater
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Joined: Wed Feb 04, 2015 6:38 pm

Using the NEON vmvn instruction

Sat Jul 20, 2019 10:21 pm

I want to invert 256 bits in memory, so I tried:-

Code: Select all

ldp  q0,q1,[x0]
vmvn q0,q0
vmvn q1,q1
stp  q0,q1,[x0]
But the assembler is rejecting it (called inline from C).

Error: unknown mnemonic `vmvn' -- `vmvn q0,q0'

Yet its in the ARMv8_ARM.

Is this a bug or have I missed something obvious?

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Paeryn
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Location: Sheffield, England

Re: Using the NEON vmvn instruction

Sun Jul 21, 2019 2:59 am

jahboater wrote:
Sat Jul 20, 2019 10:21 pm
I want to invert 256 bits in memory, so I tried:-

Code: Select all

ldp  q0,q1,[x0]
vmvn q0,q0
vmvn q1,q1
stp  q0,q1,[x0]
But the assembler is rejecting it (called inline from C).

Error: unknown mnemonic `vmvn' -- `vmvn q0,q0'

Yet its in the ARMv8_ARM.

Is this a bug or have I missed something obvious?
IIRC, in AArch64 it's just MVN q0, q0, you only need to prefix it with a V in AArch32.
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jahboater
Posts: 4595
Joined: Wed Feb 04, 2015 6:38 pm

Re: Using the NEON vmvn instruction

Sun Jul 21, 2019 7:32 am

Thanks,

It doesn't like that either :(

Error: operand 1 must be an integer register -- `mvn q0,q0'

Edit:

Looks like the intrinsic vmvnq_u8() emits NOT v0.16b,v0.16b which works, but disagrees with the ARMv8_ARM, or at least my copy of it. Without the V prefix as you suggested.

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DavidS
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Re: Using the NEON vmvn instruction

Mon Jul 22, 2019 2:37 am

Having tested with 3 different assemblers, it looks like your issue is your choise of assembler.

Not sure if the compiler you are using gives an option for the assembler, though you may want to try a different assembler as the output of your compiler.
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jahboater
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Joined: Wed Feb 04, 2015 6:38 pm

Re: Using the NEON vmvn instruction

Mon Jul 22, 2019 8:53 am

DavidS wrote:
Mon Jul 22, 2019 2:37 am
Having tested with 3 different assemblers, it looks like your issue is your choice of assembler.
Thanks.
I think so too, or rather its targeting the wrong platform, or the wrong FPU (vfp?)
Which may be a problem with the compiler, or how I built it.
The assembler gets:-

.arch armv8-a+crc

and NEON is part of ARMv8.

Are you saying that with these other three assemblers, that VMVN Q1,Q1 works as described in the ARMv8_ARM?

According to the ARM_ARM there is no NOT neon instruction, yet "as" accepts it. Hmmm

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Paeryn
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Location: Sheffield, England

Re: Using the NEON vmvn instruction

Mon Jul 22, 2019 12:05 pm

Neon doesn't have an explicit VNOT in AArch32 but the description for VMVN says "Vector Bitwise NOT". In AArch64 it does though it says it MVN(vector) is an alias of NOT(vector) and is the preferred representation.

AArch64 description:
Vector variant
MVN <Vd>.<T>, <Vn>.<T>
is equivalent to
NOT <Vd>.<T>, <Vn>.<T>
and is always the preferred disassembly.

Possibly as is allowing NOT as an alias and encoding it as VMVN.
She who travels light — forgot something.

jahboater
Posts: 4595
Joined: Wed Feb 04, 2015 6:38 pm

Re: Using the NEON vmvn instruction

Tue Jul 23, 2019 7:39 am

You are right. "mvn" and "not" produce the same instruction.

Where did you see that? I couldn't find it in the ARMv8_ARM.

Edit: found it - C7.2.192 and C7.2.195
Don't know why I missed that.

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