btauro
Posts: 30
Joined: Fri Jan 12, 2018 3:11 am

Translation Table 64 kb

Sat Feb 10, 2018 7:58 pm

I have been trying to set up page tables using 64 KB page size with three levels.However for some reason if i have my ttbr0 point to level 2 it works just as in circle 64 but if i create level1 and have ttbr0 point to level 1 it does not.I have gone through the system registers but i did not find any reason why this could happen.


Level 1 starts at 00000
Level 2 starts at 010000 Maps 3 enteries of 512 MB
Level 3 starts at 020000 8192 Entries of 64 KB


If i have ttbr0_el1 point to level 2 base address it works but if it points to level1 it does not.

I have realized it is something to do with t0sz value if i set it to 16 it works but earlier it was set to 32 causing the problem

The documentation mentions a range for t0z vaues for lookup in each level
giving any number within the range is fine or each number has a signficance in t0sz?

What could be the reason ?

bzt
Posts: 160
Joined: Sat Oct 14, 2017 9:57 pm

Re: Translation Table 64 kb

Tue Feb 13, 2018 3:14 am

Hi,

You are on the right path :-) It's definitely the T0SZ you need to thinker with. Try to read again the docs and understand the relation between these things. The virtual address is splitted up into distinct bitchunks depending on the page size and the number of levels in translation tables. Every level takes pagesize/table entry size bits, and the last n bits are reserved for page offset. For example with 4096 bit you'll need 9 bits for each level (because 4096/8=512 and 2^9=512) and the last 12 bits are reserved for offset. With 64k pages that's 13 bits (65536/8=8192 and 2^13=8192) for each level and 16 bits for offset:

Code: Select all

....22222222222221111111111111oooooooooooooooo
      |                    |             \_offset within the page
2. level selector bits   1. level selector bits 
My example is a bad one because the levels are numbered the other way around; starting from the T0SZth bit (level 1) and 16th bit belongs to level n. Also I'm very tired and maybe I miscalculated, but you can trust the theory. This is the simplest case btw, with AArch64 MMU you have a lot more options, for example you can concatenate tables (using bigger tables than a page size for a level). Also keep in mind that not all 64 bits are implemented on a certain MMU. The address space size (56 bits, 48 bits, 36 bits etc.) can be queried from the appropriate system register.

There are good documentations on this (other than the DDI spec, which has really nice and understandable figures imho), with comparison tables for page sizes and minimum/maximum T0SZ values. I can't remember the url right now but I'm sure I've already posted links to them on this forum.

Good luck,
bzt

btauro
Posts: 30
Joined: Fri Jan 12, 2018 3:11 am

Re: Translation Table 64 kb

Fri Feb 16, 2018 7:30 am

Thank you for helping me out :D

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