Page 2 of 3
Re: What can I do with my FPGA/CPLD Raspberry hardware
Posted: Sat Jan 31, 2015 8:44 am
by Shrek
Downloaded this example file:
pi@Rosrasp-1 ~/gcc $ wget
https://sites.google.com/site/semillero ... pio/main.c
File did not compile, since the bcm2835.h library was not available: Here's how to download it:
pi@Rosrasp-1 ~/gcc $ wget
http://www.airspayce.com/mikem/bcm2835/ ... .38.tar.gz
Unzip it
pi@Rosrasp-1 ~/gcc $ gunzip bcm2835-1.38.tar.gz
Check it
pi@Rosrasp-1 ~/gcc $ tar -tvf bcm2835-1.38.tar
Extract it
pi@Rosrasp-1 ~/gcc $ tar -xvf bcm2835-1.38.tar
Re: What can I do with my FPGA/CPLD Raspberry hardware
Posted: Sat Jan 31, 2015 9:30 pm
by Shrek
Learned a little more about compiling with gcc. Need to specify library with -l option.
Re: What can I do with my FPGA/CPLD Raspberry hardware
Posted: Sat Jan 31, 2015 10:59 pm
by Shrek
A 5 second video of the coolrunner CPLD acting as LED driver for the Raspberry PI
http://youtu.be/gtsBno864Zs
There are two diodes blinking. One is one bit of 30 in a counter that is connected to the 8 MHz clock input on the coolrunner, and the other LED is just the GPIO on the Raspberry being routed through the CPLD, coming in on connector J1, pin 1
Code: Select all
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity top is
Port (
clock8MHz : in STD_LOGIC;
led : out STD_LOGIC_VECTOR (3 downto 0);
sw0 : in STD_LOGIC;
sw1 : in STD_LOGIC;
bt0 : in STD_LOGIC;
bt1 : in STD_LOGIC;
j1_1 : in STD_LOGIC
);
end top;
architecture Behavioral of top is
signal clk_div : STD_LOGIC;
signal reset : STD_LOGIC;
signal clock : STD_LOGIC;
signal count : STD_LOGIC_VECTOR ( 29 downto 0);
signal raspi_comm : STD_LOGIC;
begin
reset <= not bt0;
clock <= clock8MHz;
raspi_comm <= j1_1;
select_0 : process(reset, clock) begin
if reset = '1' then
count <= "000000000000000000000000000000";
led(2 downto 0) <= "111";
elsif rising_edge (clock) then
count <= count + 1;
led(0) <= not count (22);
led(2 downto 1) <= "11";
end if;
end process select_0;
led(3) <= not raspi_comm;
end Behavioral;
Re: Experiments with Raspberry + FPGA/CPLD
Posted: Sun Feb 01, 2015 9:01 am
by Shrek
Thread renamed to Experiments with Raspberry + FPGA/CPLD
Downloaded and installed another c library for controlling gpio pins: WiringPi
http://wiringpi.com/
More commands that I do not really know too much about:
- sudo apt-get install git-core
git clone git://git.drogon.net/wiringPi
cd wiringPi
git pull origin
./build
Re: Experiments with Raspberry + FPGA/CPLD
Posted: Sun Feb 01, 2015 9:13 am
by Shrek
Now I have a basic connection from RasPi to Coolrunner by setting output pins high or low.
Next step will be to transfer bitstreams in some way, I.E. serial communication.
Could for example send a bitstream through the coolrunner where it would be xor'ed with an encryption string, for a very secure home made enigma machine.
Problem with serial comms is that you in most cases must have to syncronize a clock and a data signal, and make sure that the operating system of the RasPi does not decide to put you to sleep in the middle of a transfer and make a mess of everything.
Re: Experiments with Raspberry + FPGA/CPLD
Posted: Wed Feb 04, 2015 8:20 pm
by Shrek
I have studied and coded a bit on the coolrunner card, trying to make a nice PWM led dimmer configuration for the CPLD.
Main components:
1. 30 bit counter running from the 8 MHz input clock pin. Bit 23 of this counter toggles at close to 1 Hz, and is a nice clock signal for testing and debugging the other processes.
2. Set process, counts up and down a 16 bit counter that determines the pulse width based on two pushbuttons, called width.
3. Fast PWM process running from clock counter bit 10, i.e. 8 KHz clock that drives the LED outputs
4. Slow PWM process that causes a nice 'beat' pulse on the LED's.
Next step is to replace the buttons on the Coolrunner cards with a little C program so that the LED's can be dimmed remotely.
Code: Select all
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
use IEEE.NUMERIC_STD.ALL;
entity top is
Port (
clock8MHz : in STD_LOGIC;
led : out STD_LOGIC_VECTOR (3 downto 0);
sw0 : in STD_LOGIC;
sw1 : in STD_LOGIC;
bt0 : in STD_LOGIC;
bt1 : in STD_LOGIC;
j1_1 : in STD_LOGIC
);
end top;
architecture Behavioral of top is
signal reset : STD_LOGIC;
signal clock : STD_LOGIC;
signal count : STD_LOGIC_VECTOR ( 29 downto 0);
signal width : STD_LOGIC_VECTOR (3 downto 0);
--signal pulse : STD_LOGIC_VECTOR (7 downto 0);
signal clk_div : STD_LOGIC;
signal beat_clk : STD_LOGIC;
signal pulse_clk : STD_LOGIC;
signal pwm_clk : STD_LOGIC;
signal output: STD_LOGIC;
signal beat : STD_LOGIC;
signal raspi_comm : STD_LOGIC;
signal longer : STD_LOGIC;
signal shorter : STD_LOGIC;
begin
reset <= sw0;
clock <= clock8MHz;
raspi_comm <= j1_1;
longer <= not bt0;
shorter <= not bt1;
clockdivider_0 : process(reset, clock) begin
if reset = '1' then
count <= "000000000000000000000000000000";
elsif rising_edge (clock) then
count <= count + 1;
end if;
end process clockdivider_0;
clk_div <= count(23);
pulse_clk <= count(20);
beat_clk <= count(18);
pwm_clk <= count (10);
blink_0 : process(clock) begin
if rising_edge (clock) then
if sw1 = '1' then
end if;
end if;
end process blink_0;
led(0) <= not (output); -- Counter bit 23, 8 Mhz/2^23 = 0.95 Hz
led(2) <= not (output);
led(1) <= not (output);
led(3) <= not (output);
set_0 : process(reset, pulse_clk)
begin
if reset = '1' then
width <= "0000";
elsif rising_edge(pulse_clk) then
if longer = '1' then width <= width + 1; end if;
if shorter = '1' then width <= width - 1; end if;
end if;
end process set_0;
pwm_0 : process(reset, pwm_clk)
variable pulse : integer range 0 to 15;
begin
if reset = '1' then
pulse := 0;
output <= '0';
elsif rising_edge (pwm_clk) then
if pulse <= width then
if width = 0 then
output <= '0';
pulse := pulse + 1;
else
output <= '1';
pulse := pulse + 1;
end if;
elsif pulse = 15 then
pulse := 0;
else
output <= '0';
pulse := pulse + 1;
end if;
end if;
end process pwm_0;
pwm_1 : process(reset, beat_clk)
variable pulse : integer range 0 to 15;
begin
if reset = '1' then
pulse := 0;
beat <= '0';
elsif rising_edge (beat_clk) then
if pulse <= 2 then
beat <= '1';
pulse := pulse + 1;
elsif pulse = 15 then
pulse := 0;
else
beat <= '0';
pulse := pulse + 1;
end if;
end if;
end process pwm_1;
end Behavioral;
Re: Experiments with Raspberry + FPGA/CPLD
Posted: Wed Feb 04, 2015 8:47 pm
by jbeale
Very interesting to read of the Xilinx Coolrunner experiments! I have a few of the cheap Dangerousprototypes CoolRunner-II XC2C64A CPLD boards lying around. Currently I'm playing with a Spartan-6 FPGA board, just delivered from a Kickstarter last year:
https://www.kickstarter.com/projects/18 ... asy-to-use (the hardware is delivered; the "easy to use IDE" not yet).
It's so nice to make a large fast counter register that is 100% real time, never to be interrupted by someone else's process, bus contention, whatever. So far I have a 32 bit counter working at 250 MHz clock rate and a 32-bit shift register to read it out via SPI. By the way, can R-Pi read a 32-bit SPI transaction in one gulp? I found the "Teensy 3" 32-bit ARM Cortex M4 Arduino-compatible board can only do 8 or 16 bit mode SPI in hardware. For now I have an ATmega328p Arduino doing sofware SPI (slave mode), that works ok with a slow 10 kHz SPI clock.
Re: Experiments with Raspberry + FPGA/CPLD
Posted: Thu Feb 05, 2015 8:02 am
by Shrek
jbeale wrote:
It's so nice to make a large fast counter register that is 100% real time, never to be interrupted by someone else's process, bus contention, whatever. So far I have a 32 bit counter working at 250 MHz clock rate and a 32-bit shift register to read it out via SPI. By the way, can R-Pi read a 32-bit SPI transaction in one gulp? I found the "Teensy 3" 32-bit ARM Cortex M4 Arduino-compatible board can only do 8 or 16 bit mode SPI in hardware. For now I have an ATmega328p Arduino doing sofware SPI (slave mode), that works ok with a slow 10 kHz SPI clock.
Glad if someone can get inspiration! And I agree, I never really had any big fascination of the way too complex world of operating systems and shared resources.
I guess reverse bit-banging from hardware into a raspberry is difficult if you have no way to know if the the processor is listening or not. That is one experiment high on the list, but first I will simplify the process of controlling rather than reading the raspberry IO pins by looking at the pointer addressing in the downloaded driver library. (This is driven by my goal of writing the cpld image directly from the raspberry instead of by USB)
Re: Experiments with Raspberry + FPGA/CPLD
Posted: Thu Feb 05, 2015 8:26 am
by Shrek
jbeale wrote:Very interesting to read of the Xilinx Coolrunner experiments! I have a few of the cheap Dangerousprototypes CoolRunner-II XC2C64A CPLD boards lying around. Currently I'm playing with a Spartan-6 FPGA board, just delivered from a Kickstarter last year:
https://www.kickstarter.com/projects/18 ... asy-to-use (the hardware is delivered; the "easy to use IDE" not yet).
"The Scarab IDE only requires the Xilinix ISE Design Tool to be installed on your machine. "
Hilarious. There is no such thing as 'only' ISE

But I have to say, now that it is up and running, it works just fine to compile one VHDL file and write it to the Coolrunner.
Re: Experiments with Raspberry + FPGA/CPLD
Posted: Fri Feb 06, 2015 9:21 pm
by Shrek
Starting to look at how GPIO pins are handled in various languages and ways.
http://elinux.org/RPi_Low-level_peripherals
First some pin confusion. In my c file is used two commands (using bcm2835.h library)
#define PIN RPI_GPIO_P1_11 and bcm2835_gpio_write(PIN, HIGH);
This actually refers to pin 11 on the 26 pin P1 connector, which is GPIO pin 17.
The 26 pin P1 connector is of course numbered as 13 rows of 2 pins, instead of 2 rows of 13 pins
(Which is of course because these connectors are traditionally used for flat-cable connectors, and the
pins correspond to the numbering of the flat cable wires)
A digital multimeter is of course the easy way to find the live pin...
Re: Experiments with Raspberry + FPGA/CPLD
Posted: Sat Feb 07, 2015 9:45 am
by Shrek
I like this text on GPIO in C++ at
http://hertaville.com/2012/11/18/introd ... gpio-in-c/
In this blog entry I will demonstrate how one can access the Raspberry Pi’s GPIO in C++. There are two approaches to accomplish this. The first is to directly manipulate the Raspberry Pi’s GPIO’s registers much like one would do when programming a microcontroller without an operating system (OS) or a memory management unit (approach using mmap). The advantage of this approach is that because the OS (Linux) is being completely bypassed, the GPIO pins can toggle very fast. Bypassing the OS however means that if two processes (instances of a programs) are trying to access the same physical GPIO registers at the same time, a unsafe resource conflict can happen.
I like this. For me, the raspberry will be treated as a microcontroller with a unix-terminal on board.
The second approach is the “Linux approach” (sysfs). Linux already has a built-in driver for safely accessing the GPIOs. It basically views each property of each GPIO pin as a file. This is the preferred method of GPIO access. One disadvantage of this approach is that it tends to make for slower (but safer) GPIO pin toggling. ... This approach will be used in this tutorial. The file accesses will be wrapped in a C++ class to make GPIO access easy and foolproof (sort of).
Foolproof? Now that is for software and informatics majors. I'm into hardware, where stuff stops working when you let out the blue smoke...
Re: Experiments with Raspberry + FPGA/CPLD
Posted: Sat Feb 07, 2015 11:37 am
by Shrek
The first thing any GPIO enthusiast needs is the ability to switch on and off a light bulb and the coffee machine
in the morning. Basically internet of things. In the good old days, one would use a switch timer from the hardware store, but
not these days, that's so last century...
The guys over at openenergymonitor has a design that could work:
http://openenergymonitor.org/emon/node/841
Re: Experiments with Raspberry + FPGA/CPLD
Posted: Sat Feb 07, 2015 11:43 am
by Shrek
The key to having a Raspberry controlling a mains appliance is a Triac, and the openenergymonitor guys
has found the right component to bridge the gap between the 3-5 volt Raspberry world and the 110-220 volt appliance
world. The key is the MOC 3041 component from Motorola, complete with internal galvanic separation (
http://www.sos.sk/a_info/resource/d/moc304x.pdf).
Re: Experiments with Raspberry + FPGA/CPLD
Posted: Sat Feb 07, 2015 11:58 am
by Shrek
The beautifulness of this MOC3041 component is that it can take the concept of 'your Pi/Arduino/CPLD/ARM blinks a led' further.
Just make a small LED inside the MOC3041 flash instead, and then this tiny light source control a transistor which control a Triac that switches the light in your roof or your vacuum cleaner. All this to be done remotely thru linux terminal on my android tablet.
Re: Experiments with Raspberry + FPGA/CPLD
Posted: Sat Feb 07, 2015 5:02 pm
by davidcoton
Mains projects again!
Just remember, in the UK ALL fixed mains wiring should comply with Wiring Regs (BS7671) Seventeenth Edition, 3rd Amendment just published. That includes correct use of earthed or double insulated enclosures for all components connected to mains voltage, use of correct double-pole isolators, etc. Many other countries have equivalent rules, though the details differ.
If that doesn't make sense to you, either don't try or consult an electrician. Penalties for getting it wrong range from fried Pi through shock and burnt buildings to death.
Re: Experiments with Raspberry + FPGA/CPLD
Posted: Sat Feb 07, 2015 6:00 pm
by Shrek
davidcoton wrote:Mains projects again!
Just remember, in the UK ALL fixed mains wiring should comply with Wiring Regs (BS7671) Seventeenth Edition, 3rd Amendment just published. That includes correct use of earthed or double insulated enclosures for all components connected to mains voltage, use of correct double-pole isolators, etc. Many other countries have equivalent rules, though the details differ.
If that doesn't make sense to you, either don't try or consult an electrician. Penalties for getting it wrong range from fried Pi through shock and burnt buildings to death.
No worry. I'm in Norway, the only country in addition to Albania that has IT power distribution. Despite this country being more nazi on electrical installations than everyone else, we are still allowed to install a cheap dimmer on a lamp chord of lamp that is not part of a permanent installation. No PI's will be damaged in this eventual procedure.
Re: Experiments with Raspberry + FPGA/CPLD
Posted: Sat Feb 07, 2015 6:15 pm
by davidcoton
Two points:
1) I'm not aiming my comments just at the OP (Shrek), who may well know what he is doing. But many other readers may think that your circuit is a neat idea (true) without understanding the implications of working with mains electricity.
2) There is a big difference between installing a (properly designed and built) accessory and building your own interface to mains equipment.
Re: Experiments with Raspberry + FPGA/CPLD
Posted: Sat Feb 07, 2015 6:46 pm
by jbeale
I've been doing electronics for about 40 years, mostly digital and analog low-voltage, although I've worked with mains and some HV up to 40 kV. I am still uneasy about anything over 24 V; working with mains really demands caution and respect. It needs a totally different mindset than plugging 5V or 3V3 circuits into a breadboard.
If I wanted to switch AC power on and off (and here it's "only" 120 Vac) I would first try something like this:
http://www.adafruit.com/product/268
Re: Experiments with Raspberry + FPGA/CPLD
Posted: Sat Feb 07, 2015 9:03 pm
by Shrek
That is a nice product. I'll keep it in mind. Any high-voltage projects is far ahead. For now I am only doing low-tension stuff, as I am still figuring out how to do write the cpld configuration file to the jtag interface from the R-PI, as in this thread that I mentioned earlier:
http://www.raspberrypi.org/forums/viewt ... 41&t=51293
Re: Experiments with Raspberry + FPGA/CPLD
Posted: Sat Feb 07, 2015 9:57 pm
by Shrek
Downloaded the Guzunty package, and found the jtag setup code in the ports.c file
Code: Select all
#define JTAG_TDI 23
#define JTAG_TCK 17
#define JTAG_TMS 24
#define JTAG_TDO 22
void portsInitialize()
{
if (!bcm2835_init()) {
printf("\nError initializing IO. Consider using sudo.\n");
exit(1);
}
bcm2835_gpio_fsel(JTAG_TDI, BCM2835_GPIO_FSEL_OUTP);
bcm2835_gpio_set_pud(JTAG_TDI, BCM2835_GPIO_PUD_OFF);
bcm2835_gpio_fsel(JTAG_TCK, BCM2835_GPIO_FSEL_OUTP);
bcm2835_gpio_set_pud(JTAG_TCK, BCM2835_GPIO_PUD_OFF);
bcm2835_gpio_fsel(JTAG_TMS, BCM2835_GPIO_FSEL_OUTP);
bcm2835_gpio_set_pud(JTAG_TMS, BCM2835_GPIO_PUD_OFF);
bcm2835_gpio_fsel(JTAG_TDO, BCM2835_GPIO_FSEL_INPT);
bcm2835_gpio_set_pud(JTAG_TDO, BCM2835_GPIO_PUD_OFF);
}
Re: Experiments with Raspberry + FPGA/CPLD
Posted: Sun Feb 08, 2015 8:26 pm
by Shrek
I have to find a tool for transfering the config file for the coolrunner cpld to the raspberry.
1. cwrsync, a linux style rsync command for windows. What a painful version of what could have been a useful tool for windows.
2. Filezilla from the official sourceforge page. Possibly good, but full of other crappy stuff. I tried to deselect all crapware options, but still got an installation of "Optimizer Pro" that instantly started scanning/shouting/complaining about how slow my computer is... Hope I did not get any other infections.
Re: Experiments with Raspberry + FPGA/CPLD
Posted: Sun Feb 08, 2015 8:35 pm
by Shrek
The gz_load utility seems to expect an XSVF file, but so far I have been working with a JED file from the xilinx ISE tool.
http://www.xilinx.com/itp/xilinx10/iseh ... f_file.htm
You can use the output from the Generate Programming File process, a JED or ISC file, to create an SVF, XSVF, or STAPL (JTAG) file that can be downloaded into the CPLD’s memory cells. SVF, XSVF, and STAPL files are used to relay JTAG information, such as verification of data and in-circuit-testing instructions, and programming data.
Re: Experiments with Raspberry + FPGA/CPLD
Posted: Sun Feb 08, 2015 8:50 pm
by Shrek
The JTAG pins on the Coolrunner is properly designed, so I will just point-and-connect according to the
gz_load source code:
#define JTAG_TDI 23
#define JTAG_TCK 17
#define JTAG_TMS 24
#define JTAG_TDO 22
Re: Experiments with Raspberry + FPGA/CPLD
Posted: Sun Feb 08, 2015 9:17 pm
by Shrek
Launching the gz_load utility with my fresh .xsvf file gave
nothing but two lines of text. No apparent progress or any errors:(
pi@Rosrasp-1 ~/gcc/Guzunty/src/gz_load $ sudo ./gz_load test1.xsvf
Guzunty loader v5.01 rev 2, portions courtesy Xilinx, Inc.
XSVF file = test1.xsvf
pi@Rosrasp-1 ~/gcc/Guzunty/src/gz_load $
Re: Experiments with Raspberry + FPGA/CPLD
Posted: Sun Feb 08, 2015 9:18 pm
by Shrek
The max verbose option does not give any clues:
Code: Select all
pi@Rosrasp-1 ~/gcc/Guzunty/src/gz_load $ sudo ./gz_load test1.xsvf -v 4
Guzunty loader v5.01 rev 2, portions courtesy Xilinx, Inc.
XSVF file = test1.xsvf
Verbose level = 4
Progress indicator: | sizeof( SXsvfInfo ) = 300 bytes
XREPEAT = 0
XSIR length = 8
XSIR length = 8
XSIR length = 8
XSIR length = 8
XSIR length = 8
XSIR length = 8
XSIR length = 8
XSIR length = 8
XSIR length = 8
XSIR length = 8
XSIR length = 8
XSIR length = 8
- XSIR length = 8
XSIR length = 8
XSIR length = 8
XSIR length = 8
XSIR length = 8
XSIR length = 8
XSIR length = 8
----- XSIR length = 8
XSIR length = 8
XSIR length = 8
XSIR length = 8
XSIR length = 8
XSIR length = 8
XSIR length = 8
XSIR length = 8
XSIR length = 8
XSIR length = 8
XREPEAT = 0
- XREPEAT = 32
XSIR length = 8
pi@Rosrasp-1 ~/gcc/Guzunty/src/gz_load $