For those who have not actually ever produced a chip before I'd say the absolute minimum spend would be approx $80,000 for a V simple SoC . You would get a about 20 devices.
Here is a very rough outline of the stuff that goes on for the Software Only guys and gals here (for those who are in the game huge swathes of stuff have been omitted for brevity, please do not shoot me).
Writing your design docs.
Writing your design (including Design For Test capability)
Compiliation, Simulation/Testing of your design (Assuming you can get tools but there are ways !
Synthesizing your design into a 'target library', The Target Library represents what the logic gates will look like as transistors on the kind of silicon you want to use. The tools are V expensive and these days you sometimes have to pay for the library'.
Placing and Routing the generated logic, ie taking the transistors and laying them out so that the design times, again tools are V expensive and this is generally farmed out to a 3rd party if you are a small company.
In parallel to all of this you are generating your Test Program so you can test the devices you have made, again this can be farmed out, especially if you have no knowledge of the tester, this uses the Design for Test stuff you put into your code.
Once you are out of Place and Route you need to make sure that the design still works and importantly 'times', ie it can go fast enough when it's hot with low voltage and curiously not go tooo fast when it's very cold and lot's of voltage (look up Hold Violations).
Once all of that has been shown to be ok you send it off in a process called 'Tape Out'. Designs used to be sent out as Magnetic Tape Reels to the Fabrication Plant.
At the Fabrication plant comes the creation of the individual masks for each layer, this is effectively shared for a Multi Project Wafer run, ie lots of people are trying out their design so effectively sharing the costs. It's a lot more expensive for a single design wafer of silicon.
Once the wafer has been made you then apply your test program to each of the 'chips' or as they are known 'die' to sort out what ones you want to package.
Then comes your packaging which means encapsulating and bonding of IO to the pins of the encapsulation.
Then you hope and pray you don't have sand when it comes back to you !
And just to show that Men can multi task while writing that I've taught a 6yr old to draw a face (big fat bum at the top smaller fat bum at the bottom), destressed a partner and got organised to attend a wedding reception ! Who says we Engineers can't get the job done to a time line !