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VLSI Design (45nm/14nm nodes) with your Pi4 ?? (!)

Tue Mar 10, 2020 9:41 pm

VLSI Design (45nm/14nm nodes) with your 55$ Pi4-4 or your 35$ PI4-2 ???

Sounds crazy ???

Indeed it sounds crazy - and it is doable (!) ... with kindly help from arm, Qualcomm, DARPA, University of California San Diego, Brown University, University of Mitchigan, University of Minnesota, .....

This post is about an open source VLSI-design-Toolchain: "The OpenROAD-Project"

Basically it is a toolchain "Plain verilog to final masks" (details on request) and one or more "Process Development Kits" (PDKs). The later one is contributed by the Founderies (e.g. TSMC or Globalfounderies) and very specific for the process and the node. Even for educational use those commercial PDKs aren't open source - a NDA is required. To overcome with this a "generic" open source 45-nm PDK is here used (Nangate45 / FreePDK45 with somewhat simpified Design Rules)

Be warned:
Currently the project is in alpha - so it is a moving (!) target (beta is planed for mid 2020)

Anyway - its time to test it.

I have done so on my Pi4-4 (ubuntu 19.10 server headless, should also work on Pi4-2)

(1) build boost (>=1.68), takes time, be patient
(2) install further requirements for the openROAD-toolchain
(3) build toolchain from source, takes time, be patient
( https://github.com/The-OpenROAD-Project ... aster/flow )
(4) build klayout from source, takes time, be patient
( https://www.klayout.de/build.html )

There are ready to run verilog-example :

By very far the simplest one is the gcd ("greatest common donominator", the "Hello Word"-equivalent in the VLSI world) It is used to test the sanity of the toolchain-flow.

Here is the final 45nm-mask-layout (viewed with klayout):
gcd10farben.png
gcd10farben.png (18.09 KiB) Viewed 1197 times

Ok. Next step. There are other ready-to-run more "real" examples:

1) AES (Rijndael) IP Core,
verilog to 45nm-masks: takes my PI4-4 about 30 minutes

2) Dynamic Node (for a 2d-mesh-NoC, verilog source contributed by Princeton University)
verilog to 45nm-masks: takes my Pi4-4 about 20 minutes

A bunch of riscV-cores :

a) Tiny Rocket (minimal rocket, about 30,000 cells, verilog source contributed by Ben Keller)
verilog to 45nm-masks flow: takes my Pi4-4 about 50 minutes

b) swerf wrapper (verilog source RISC-V-EH1 Core 1.1 from Western Digital)
verilog to 45nm-masks flow: takes my Pi4-4 about 5:15 hours, be patient (!)

c) bp_multi_top (Black Parrot, Full 64-bit RISC-V Core with Cache Coherence Directory)
verilog to 45nm-masks flow: takes my Pi4-4 about 4:30 hours, be patient (!)

d) .....
...


bp-multi-top-overviewgray-iniz-1bit.png
bp-multi-top-overviewgray-iniz-1bit.png (13.66 KiB) Viewed 1197 times


Full 64-bit RISC-V Core with Cache Coherence Directory, note the white rectangles - this are areas reserved for ram-arrays.
Viewed with klayout



bp-multi-top-detail-zoom.png
bp-multi-top-detail-zoom.png (22.22 KiB) Viewed 1197 times
Full 64-bit RISC-V Core with Cache Coherence Directory,
Viewed with klayout. Zoom-in - note the placed buffers, DFFs, AOIs ...
vias are shown, routing not shown - for clearity

Importent note:

"The-OpenROAD-Project" is meant as a research and education tool and
not (at least in its current state) as a substitute for commercial tools.
For shure our friends at Broadcom will continue to use Cadence tools - on 40 core / 256 GByte Ram machines.

To be very clear ..

Repetition :
"The-OpenROAD-Project" is meant as a research and education tool and
not (at least in its current state) as a substitute for commercial tools.

That said, there is ongoing work on OpenROAD tools interface to Global Foundries GF 14nm node PDK (with thousands of design rules).

mic_s
.

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Re: VLSI Design (45nm/14nm nodes) with your Pi4 ?? (!)

Wed Mar 11, 2020 10:29 am

Ok – we have proved it :
VLSI-designs (500000 gates, 690 pads) can be made with your low-cost 55 $ - Pi4.

But … what about production ?
Who will produce our chips in very, very small quantities (may be only one) at reasonable price points ?

Thats a good question.

Today it is quite common in the PCB-world, to send your Gerber-files to a provider and receive the (may be populated) PCBs. In the long run (e.g. 5-10 years) it may be possible to send your *.gds2-files to a provider, who produce your chip, pack it and send it to you.

That said, the current business model of the large Foundries (e.g. Globalfoundries, TSMC) doesn't allow for very small quantities. This will be changed - in the long run.

In the meantime a Multi-Project-Wafer (MPW) may be an alternative - especial for educational Institutions (Universities …). Example: Skywater (formerly a Cypress Semiconductor fab) in Bloomington, MN, USA provides a MPW-service for their 130 nm-node. So it makes sense, to ingtate the related PDK into the mentioned open source VLSI toolchain.

Isn't the 130nm-node technology outdated for a long time ?

Yes and NO.
Yes, it is technology from 2000.
NO, because it depends on your needs.
(Btw AMD's Opteron Sledgehammer and Intel's Celeron Northwood-128 are 130 nm node technology)

Anyway, for the hobbyist there is today(!) no way to get his self-designed medium complex VLSI chip (500000 gates, 680 pins) for a reasonable price (say 10-20 US$)

But the very first steps are done (Ebdon would call it: „Baby Steps“)

mic_s
.

Heater
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Re: VLSI Design (45nm/14nm nodes) with your Pi4 ?? (!)

Wed Mar 11, 2020 1:43 pm

I had a chat about this over beers with a chip designer in Mountain View a couple of years ago. He suggested the best thing to do is become friends with some guys in a university EE department and have them sneak your design into their next multi-project shuttle run. Some departments are cranking out their students chip designs all the time.
Memory in C++ is a leaky abstraction .

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Re: VLSI Design (45nm/14nm nodes) with your Pi4 ?? (!)

Fri Mar 13, 2020 3:04 pm

Heater wrote:
Wed Mar 11, 2020 1:43 pm
Some departments are cranking out their students chip designs all the time.
Yes, you are right.
This is an obvious option. I'm not aware of any EE-department not using it.

BTW Most of them (if not all) use commercial Cadence /Mentor Graphic Tools. This is (besides the exorbitant fees) not an option for PI-4 owners.

That being said, „The-OpenROAD-Project“ may be able to use DARPA resourses. The Project is sponced by DARPA. I mentioned SkyWater Technologies – there is a good reason for this: SkyWater is in strong relation to DARPA – last year they receive about 170 Mill. US$ from DARPA and may be prepared to help with first real tapeout … 2020/2021

An interesting and may be astonishing (and somewhat offtopic) sidenote :

From the maker scene a DIY homemade (!) IC :
http://sam.zeloof.xyz/first-ic

From the maker scene DIY homemade (!) Maskless Lithography :
http://sam.zeloof.xyz/maskless-photolithography

A more advanced Idea : Inkjet Printing of High Performance Transistors
https://nature.com/articles/s41598-017-01391-2

mic_s
.
Last edited by crossbar on Fri Mar 13, 2020 6:32 pm, edited 2 times in total.

Heater
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Re: VLSI Design (45nm/14nm nodes) with your Pi4 ?? (!)

Fri Mar 13, 2020 3:48 pm

I made a diode in 1977. A blob of silicon fused to a little silicon plate in a vacuum chamber. Whatever p/n type they were. It's characteristics were terrible.
Memory in C++ is a leaky abstraction .

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Re: VLSI Design (45nm/14nm nodes) with your Pi4 ?? (!)

Fri Mar 13, 2020 4:31 pm

crossbar wrote:
Fri Mar 13, 2020 3:04 pm
From the maker scene sceen a DIY homemade (!) IC :
https://sam.zeloof.xyz/...

From the maker scene sceen DIY homemade (!) Maskless Lithography :
https://sam.zeloof.xyz/...
Firefox wrote:Firefox detected a potential security threat and did not continue to sam.zeloof.xyz. If you visit this site, attackers could try to steal information like your passwords, emails, or credit card details.
Signature retired

crossbar
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Re: VLSI Design (45nm/14nm nodes) with your Pi4 ?? (!)

Fri Mar 13, 2020 5:16 pm

fixed. Its my fault and a common https/http problem. Use the original

http://sam.zeloof.xyz/first-ic ,
http://sam.zeloof.xyz/maskless-photolithography

and potential spying scripts will be blocked by firefox ... or don't use the links.

crossbar
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Re: VLSI Design (45nm/14nm nodes) with your Pi4 ?? (!)

Tue Jun 30, 2020 7:32 pm

As a short note :

The mentioned SkyWater's PDK "SKY130" will become open source in the next few days and ... surprise, surprise ... google will sponsor Multi-Project Wafer runs at SkyWater. This way you can get your own batch (say 100) of packed, self designed standard cell chips for free ( repeat it : 0.00 $ ) ... designed with Raspberry Pi 4 and the mentioned open source OpenROAD-Toolchain and the open source SKY130 PDK. The only restriction (i am aware of) is : Your design is under an open source license ( say: apache 2 ) and the required area is under about 10 mm2.

Ok ... this are not GF's 14 nm FINFet node, but SkyWaters 130 nm-node. Aside this, it is a start : Millions of gates for zero Dollars. For the advanced hobbyist. What's next ?

michael
.

lurk101
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Re: VLSI Design (45nm/14nm nodes) with your Pi4 ?? (!)

Wed Jul 01, 2020 3:15 pm

crossbar wrote:
Tue Jun 30, 2020 7:32 pm
this are not GF's 14 nm FINFet node, but SkyWaters 130 nm-node. Aside this, it is a start : Millions of gates for zero Dollars. For the advanced hobbyist. What's next ?
Hobbyist custom silicon! Never thought it would happen in my lifetime. Apparently I was wrong. I wonder how 130nm silicon would perform (speed/power) compared current low cost 28nm FPGA?

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Re: VLSI Design (45nm/14nm nodes) with your Pi4 ?? (!)

Wed Jul 01, 2020 3:33 pm

lurk101 wrote:
Wed Jul 01, 2020 3:15 pm
crossbar wrote:
Tue Jun 30, 2020 7:32 pm
this are not GF's 14 nm FINFet node, but SkyWaters 130 nm-node. Aside this, it is a start : Millions of gates for zero Dollars. For the advanced hobbyist. What's next ?
Hobbyist custom silicon! Never thought it would happen in my lifetime. Apparently I was wrong. I wonder how 130nm silicon would perform (speed/power) compared current low cost 28nm FPGA?
You are of course relying on Google generosity to pay the hundreds of thousands of dollars to make this work...this stuff is not free.
Principal Software Engineer at Raspberry Pi (Trading) Ltd.
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I've been saying "Mucho" to my Spanish friend a lot more lately. It means a lot to him.

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Re: VLSI Design (45nm/14nm nodes) with your Pi4 ?? (!)

Wed Jul 01, 2020 3:34 pm

crossbar wrote:
Tue Jun 30, 2020 7:32 pm
As a short note :

The mentioned SkyWater's PDK "SKY130" will become open source in the next few days and ... surprise, surprise ... google will sponsor Multi-Project Wafer runs at SkyWater. This way you can get your own batch (say 100) of packed, self designed standard cell chips for free ( repeat it : 0.00 $ ) ... designed with Raspberry Pi 4 and the mentioned open source OpenROAD-Toolchain and the open source SKY130 PDK. The only restriction (i am aware of) is : Your design is under an open source license ( say: apache 2 ) and the required area is under about 10 mm2.

Ok ... this are not GF's 14 nm FINFet node, but SkyWaters 130 nm-node. Aside this, it is a start : Millions of gates for zero Dollars. For the advanced hobbyist. What's next ?

michael
.
Do you have a link to where one can sign up for this?

I was just discussing over lunch yesterday with a colleague exactly this idea and speculating it would happen soon. My colleague did not believe me.
Memory in C++ is a leaky abstraction .

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Re: VLSI Design (45nm/14nm nodes) with your Pi4 ?? (!)

Wed Jul 01, 2020 3:52 pm

Remember, if you don't appear to be paying for a service, YOU are the product!
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Re: VLSI Design (45nm/14nm nodes) with your Pi4 ?? (!)

Wed Jul 01, 2020 4:01 pm

jamesh wrote:
Wed Jul 01, 2020 3:52 pm
Remember, if you don't appear to be paying for a service, YOU are the product!
Not always true. There are some genuine philanthropist out there and such assertions can be very damaging to them.

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Re: VLSI Design (45nm/14nm nodes) with your Pi4 ?? (!)

Wed Jul 01, 2020 4:15 pm

hippy wrote:
Wed Jul 01, 2020 4:01 pm
jamesh wrote:
Wed Jul 01, 2020 3:52 pm
Remember, if you don't appear to be paying for a service, YOU are the product!
Not always true. There are some genuine philanthropist out there and such assertions can be very damaging to them.
So, just 99.9999% true then? Are we supposed to look out for philanthropists feelings and let 99.9999% of people continue blindly on being product?

There is no such thing as a free lunch has been a phrase for time immemorial. Perhaps that one sits better with you?
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Re: VLSI Design (45nm/14nm nodes) with your Pi4 ?? (!)

Wed Jul 01, 2020 4:20 pm

You can pretty much see what google are doing here, gaining knowledge, the same as they do with emails, pictures, vidoes, sat-navs etc, in my mind its a fair price.

Fascinating thread, I never got round to upping my 3-bit "processor" built out of discrete transistors to 4-bits, the hobby has definitely moved on. I've been lucky to have existed during the golden-age of computers though a lot beyond me now. Before PLAs and the like we used EPROMs as state machines feeding the output back to the address lines, that seemed complicated at the time, its a different world now.

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Re: VLSI Design (45nm/14nm nodes) with your Pi4 ?? (!)

Wed Jul 01, 2020 4:24 pm

jamesh wrote:
Wed Jul 01, 2020 4:15 pm
There is no such thing as a free lunch has been a phrase for time immemorial. Perhaps that one sits better with you?
Not really because that's not true either :D

If anyone wants a free lunch, if they are happy to live on garden mint alone, please take as much as you want when you pass my front garden. Many have availed themselves of that free service.

Many others give away free food, grown or made, and there are are food banks and other groups which offer more substantial offerings for free.

I'm happy with "If you're not paying for it; you may be the product".

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Re: VLSI Design (45nm/14nm nodes) with your Pi4 ?? (!)

Wed Jul 01, 2020 9:44 pm

some notes:

(a) The VLSI-Toolchain "OpenROAD project" will come to beta-phase in a few weeks. Its open source, so it was easy to build it for my PI-4-4.

(b) "free" wafer - run. Yes - SkyWater is paid for it : For a limited time ( under one year) and for a limited number of wafer-runs ( up to 1 - 2 runs per month ). Its an experiment - thanks to very, very special circumstances. There is a reason i mentioned SkyWaters 130nm node in a earlier post in this thread. Think of it as the "pi-zero" equivalent in the VLSI design world. There are limitations : It's a mature technology, your chip-area is limited to 10 mm2. Details ? Details will be published when they will be published. I guess there will be more designs than seats. There will be some sort of selection.

(c) Ok, here is a video with the announcement :
https://youtu.be/EczW2IWdnOM

(d) Another question was: Why google is doing this ?
Its all about momentum. Driving the development in the right direction. For a relatively small amount of money. That's a very common idea. You already know it - it's the "pi-zero"-idea.

(e) And here is a link to the related SkyWaters 130 nm - libs:
https://foss-eda-tools.googlesource.com ... -pdk/libs/

(f) First notes on DRC (hundreds of design rules) are here :
https://github.com/google/skywater-pdk/ ... ssumptions

Be warned : This are all "living documents" in pre-pre-alpha phase.

michael
.

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Re: VLSI Design (45nm/14nm nodes) with your Pi4 ?? (!)

Wed Jul 01, 2020 11:58 pm

Timing analysis?

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Re: VLSI Design (45nm/14nm nodes) with your Pi4 ?? (!)

Thu Jul 02, 2020 12:44 am

lurk101 wrote:
Wed Jul 01, 2020 3:15 pm
crossbar wrote:
Tue Jun 30, 2020 7:32 pm
this are not GF's 14 nm FINFet node, but SkyWaters 130 nm-node. Aside this, it is a start : Millions of gates for zero Dollars. For the advanced hobbyist. What's next ?
Hobbyist custom silicon! Never thought it would happen in my lifetime. Apparently I was wrong. I wonder how 130nm silicon would perform (speed/power) compared current low cost 28nm FPGA?
Intel Pentium 4 in 2002 was made with a 130nm process node, so one would expect it to perform pretty poorly compared to a much more modern 28nm FPGA. Since 2002 is when I built a dual Opteron-240 system where the CPUs run at 1.4GHz, you can sort of see where that ought to be.

lurk101
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Re: VLSI Design (45nm/14nm nodes) with your Pi4 ?? (!)

Thu Jul 02, 2020 3:05 am

W. H. Heydt wrote:
Thu Jul 02, 2020 12:44 am
Intel Pentium 4 in 2002 was made with a 130nm process node, so one would expect it to perform pretty poorly compared to a much more modern 28nm FPGA. Since 2002 is when I built a dual Opteron-240 system where the CPUs run at 1.4GHz, you can sort of see where that ought to be.
Stratix IV FPGAs max out at around 500-600 MHz for programmable logic, with hard wired blocks for higher frequency specialized functions. The low cost FPGAs like the Cyclone series at 50-100 MHz. Haven't used Xilinx in a while so I don't know where they're at?

Interesting gambit on Google's part. I hope it includes packaging, not just the die.

UPDATE: Yes, packaging is included and each slot will receive up to 100 chips!

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Re: VLSI Design (45nm/14nm nodes) with your Pi4 ?? (!)

Thu Jul 02, 2020 5:51 am

W. H. Heydt wrote:
Thu Jul 02, 2020 12:44 am
Intel Pentium 4 in 2002 was made with a 130nm process node, so one would expect it to perform pretty poorly compared to a much more modern 28nm FPGA. Since 2002 is when I built a dual Opteron-240 system where the CPUs run at 1.4GHz, you can sort of see where that ought to be.
Hmm... my RISC V processor on a Cyclone IV maxes out at 100MHz.

So let me get the idea straight....

jamesh rightly points out that this will still cost hundreds of thosands of dollars. But this is a "multi-project" wafer. So if a hundred people turn up with their project designs they all get stamped out on the same wafer and everyone gets a 100 or chips from it. That suggests it brings the cost down to mere thousands.
Memory in C++ is a leaky abstraction .

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Re: VLSI Design (45nm/14nm nodes) with your Pi4 ?? (!)

Thu Jul 02, 2020 8:26 am

AIUI, there are only 40 slots, which I took to mean 40 projects in total. If they get more, they'll pick the winners on some unspecified criteria they'll dream up on the day, possibly including coin tosses or dice rolls.

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Re: VLSI Design (45nm/14nm nodes) with your Pi4 ?? (!)

Thu Jul 02, 2020 10:21 am

Timing analysis?
(1) Timing analysis is done in the design process. To be explicit: The OpenROAD toolchain uses Parallax Static Timing Analyzer (OpenSTA). It is a well-known open source timing analysis tool - some commercial toolchains are based on it. Anyway timing constraints are always an issue. If required buffer are inserted. Our Target node is Globalfoudries 14 nm / drawn 12 nm LP FinFET Node and TSMCs 65LP node.

(2) The mentioned 130 nm SkyWater node : GHz may be possible.
There are examples for other 130 nm and 90 nm technlogies :
(2a) 32 bit Integer ALU about 5 GHz.
(https://www.researchgate.net/publicatio ... sub_T_CMOS ).
(2b) To my knowledge the single-precession SPE-FPU in ibms well known Cell-processor was a 95 nm node design
(http://citeseerx.ist.psu.edu/viewdoc/do ... 1&type=pdf)
To be very clear, don't expect multi-GHz clock speeds for the SkyWaters evry130nm process.
I wonder how 130nm silicon would perform (speed/power) compared current low cost 28nm FPGA.
It depends on what FPGA : Most of them are based on LUTs (Xilinx, Altera). Some of them are based on Mux (e.g. Quicklogic). It also depends on the technology. Example: There are early, not very well known XILINX FPGAs based on ECL technology with clockrates in MultiGHz range.
The low cost FPGAs like the Cyclone series at 50-100 MHz.
That's what you have to pay for them to be programmable. Lets take an actual example : Certus-NX LFD2NX-40, one of the new low-cost Lattice FPGAs. The programmable part (about 40 k Cells) is at best in the low hundreds MHz, the embedded 5 Gb/s PCIe Gen2 Hardcore is obviously in the Multi-GHz.
Jamesh rightly points out that this will still cost hundreds of thosands of dollars. But this is a "multi-project" wafer.
Right - it's a MPW.
AND there are very, very special circumstances (not discussed here) so Google can sponsor runs for a limited time.
AIUI, there are only 40 slots, which I took to mean 40 projects in total.
No, there are multiple (exact number unspecified at this point) slots. Every slot is about 100-200 identical Multi-Project wafers.
Yes - as stated above - obviously the seats are limited.
If they get more, they'll pick the winners on some unspecified criteria they'll dream up on the day, possibly including coin tosses or dice rolls.
Certainly will get more. You call it "unspecified" - i call it "not very strict specified and adjustable" criteria. It opens the way for new, currently unseen design-ideas. No one knows what contributions will come. Strict specified criteria (aside from SkyWaters PDK and an open source license) would restrict the possibilities. Please note: it's all done in our spare time and for like-minded people. No problem if this isn't for you.

michael
.
back to vlsi research.
.
Last edited by crossbar on Thu Jul 02, 2020 10:36 am, edited 1 time in total.

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dickon
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Re: VLSI Design (45nm/14nm nodes) with your Pi4 ?? (!)

Thu Jul 02, 2020 10:30 am

crossbar wrote:
Thu Jul 02, 2020 10:21 am
AIUI, there are only 40 slots, which I took to mean 40 projects in total.
No, there are multiple (exact number unspecified at this point) slots. Every slot is about 100-200 identical Multi-Project wafers.
Yes - as stated above - obviously the seats are limited.
Interesting.
If they get more, they'll pick the winners on some unspecified criteria they'll dream up on the day, possibly including coin tosses or dice rolls.
Certainly will get more. You call it "unspecified" - i call it "not very strict specified and adjustable" criteria. It opens the way for new, currently unseen design-ideas. No one knows what contributions will come. Strict specified criteria (aside from SkyWaters PDK and an open source license) would restrict the possibilities. Please note: it's done all done in our spare time and for like-minded people. No problem if this isn't for you.
I'm not criticising -- I think it's a fantastic opportunity. It isn't for me -- hardware tends to annoy me; I like ones and noughts, not the woolly reality that is a lot messier than that -- but I have friends who will be interested.

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Re: VLSI Design (45nm/14nm nodes) with your Pi4 ?? (!)

Thu Jul 02, 2020 2:14 pm

@crossbar Thank you for the info. I'll definitely be submitting something and look forward to hearing how to apply.

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