Even while CAS latency increases, that basic clock speed also increases, so it's pretty much a wash. Takes longer to get a response from the DRAM module, but once you do, you get the data back faster.
Nope. Still wrong for the reasons given. SRAM is far to expensive to use as main memory.I think my initial hunch about SRAM was right?
There is another way to increase memory bandwidth. Fetch more data at one time. This is what add-in GPU cards (nVidia, Radeon) do. Anything up to 512 bits per fetch.We need faster RAM, if not the raspberry 4 is peak CPU at 1 Gflops/watt, for ever, in the universe!?
It is, coincidentally, what IBM did with mainframes in the 1960s. A 360/30 would fetch 1 byte in 1.5microseconds (us). A 360/40 had slower memory, 2us cycle time, but it would fetch 2 bytes at a time. The 360/50 had that same 2us cycle, but it fetched 4 bytes. IIRC, the top systems fetched 8 bytes at a time, still with a 2us clock speed.
IIRC, DDC4 (and possible DDR2 and DDR3) transmit data 4 times during a single clock cycle. The original DDR did it twice: Once on the rising edge of the clock and once on the falling edge.Is the memory in the raspberry 4 3200MHz or 1600MHz? Or is it 1600, but at double rate?
There certainly is. The manufacturers have to test their DRAM chips to make sure they are within specification, so they'd have to be able to test that. Doesn't mean there is a practical method to do so by an end user when it's installed in a PC. All you can do there is try tweaking the CAS (and other parameters) to see what you can get away with. However, the Pi does not have a means to do that.Is there a way to measure CAS latency?
Read the manufacturer and part number off the package on a Pi4B and then look for the specification sheet for that part. That *might* tell you what the manufacturing process node is.What nm process is the RAM?