State of GPIO pins on startup?

[Bosse_B]

I am designing a board to be plugged into the 40-pin header implementing a few interfacing circuits.
Among these are a couple of power switching relays for activation of external equipment.
I am using 2SK3018 MOSFET transistors to drive the relay coils and the MOSFET gates are hooked directly to GPOI pins with a pull-down to ensure that the transistors stay off until the GPIO pin is switched to output mode and set high.

Now I read that the RPi GPIO pins are not all set to inputs with pull-down applied or high impedance, there seems to be some pins that have pull-ups on them as well! This would mean that the external power will be applied during RPi startup and this is a no-no!

So can someone direct me to some information regarding the actual state of the pins during RPi startup and also the values of pullup/pulldown that exist on the RPi board itself for the GPIO pins?

[deepo]

Maybe you'd be safer if you add circuitry to enable output from the RPi, i.e. disconnect your MOSFETs from the RPi as long as the enable output from the RPi is not on.

You could even control the enable output from a watchdog process, so that your MOSFETs go to a known state when the watchdog detects problems.

/Mogens

[joan]

I don't think there is an official value for the internal pulls. 50 to 70 k ohms seems to be about right. The external pulls to 3V3 on GPIO 2/3 are 1k8.

The power-up state of the GPIO is documented in the Broadcom peripherals document.

[Bosse_B]

Are the CPU chip GPIO pins directly routed to the 40-pin connector without any external components connected such as pull resistors (up or down)?
I tried to find a circuit diagram but all I managed to find was a drawing that looks incomplete to me.
Is there no complete drawing available?

[davidcoton]

Are the CPU chip GPIO pins directly routed to the 40-pin connector without any external components connected such as pull resistors (up or down)?

Yes (afaik)

I tried to find a circuit diagram but all I managed to find was a drawing that looks incomplete to me.
Is there no complete drawing available?

That drawing is all that is available, even the peripherals document for the Pi4 SOC is WIP. It should be complete for all external connections you can use, but you need to know the initial internal pull state too.

There are ways of setting the GPIO on startup, though that still leaves time for incorrect peripheral responses. You need to design your circuit not to activate the outputs until your program is ready, one way is to gate the activation signals using one GPIO output whose start-up behaviour is checked to be benign, then activating that GPIO after all the outputs are configured and initialised.
Startup behaviour is a common problem area for interface design, it's not unique to the Pi.

[Bosse_B]

Breadboarding (on an RPi2B+ unit)...
I hooked up my scope to the relay pins I had selected and set it for a one-shot registration triggered on the rising edge at about 1V.
Nothing happened on a power-up, so I guess I am good here.

If I put an ID EEPROM on the board as well (connected to pins 27/28) making my design a HAT enabled board, could I then let the initialization set the pins to output with 0V level already when the CPU boots up (before Raspbian starts loading)?

That would solve the problem because the external power relays driven by the on-board small relays are pretty slow, like 5-10 ms activation time.
Even if there is a glitch lasting for say a ms or less it would do no harm.

I need to figure out how to program the data inside HAT ID EEPROM then of course...

[rpdom]

Are the CPU chip GPIO pins directly routed to the 40-pin connector without any external components connected such as pull resistors (up or down)?

Yes, apart from (as previously mentioned) GPIOs 2 and 3 (pins 3 and 5) which have the 1K8 pull-up resistors. (GPIOs 0 and 1 on very early Pi 1Bs)

[Bosse_B]

Then a 100K (or maybe as low as 10K) would suffice as pull-down to guarantee a low level input to the MOSFET until the application kicks in and sets the pins as outputs with 0V level. The pull-down must be such that the CPU can drive the GPIO pin up to 2.5V or higher for the MOSFET to switch on.
I will probably start the application from /etc/rc.local so it runs ASAP.

[rpdom]

The internal pulls are around 50K, so 10K would be fine for most pins, other then GPIO 2 and 3.