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RPi4B GPIO reading speed

Fri Jul 12, 2019 3:28 pm

I'm working on a fast IO interface using the GPIO pins to send and receive data from an FPGA. The code is written in C and uses direct GPIO register read and writes based on code found here:
I use 16 pins for data (GPIO 0 - 15) and a few for hansdshake.
The Pi seems to able to output data via the GPIOpins (writing to the output set and clear registers) much faster than it can input data by reading the level registers.
I've modified my hardware data transfer protocol to cope with this, and sending data from the FPGA to the Pi I can achieve a pretty respectable 23.4 Mbyte/s.
Reading data is not so good, since every read of the GPIO pin level register seems to stall until 528ns has elapsed since the previous read - this is about 32 cycles of the IO clock (which may or may not be significant).
So I'm limited to an input rate of about 7.57 Mbyte/s.

I'd like to know if this is what should be expected (with some more knowledge of exactly how the IO hardware works than is avaialble to me), and if there is anything that can be done to speed things up. (if that 'stall' time could be reduced to half I'd be pretty happy !).

If anyone feels they can help out I'm happy to post whatever bits of code or logic analyser traces would help. I haven't done so yet because I'm not quite sure if I'm asking in the right place.


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Re: RPi4B GPIO reading speed

Fri Jul 12, 2019 7:47 pm

Are you changing all of the bits in as few set/clr operations as possible?

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Re: RPi4B GPIO reading speed

Fri Jul 12, 2019 7:54 pm

I wonder if there is an internal debounce of the inputs going on. From what I've seen about the difference between level and edge interrupts on the SoC.

Page 98 of peripheral spec.
The falling edge detect enable registers define the pins for which a falling edge
transition sets a bit in the event detect status registers ( GPEDSn ). When the relevant
bits are set in both the GPRENn and GPFENn registers, any transition (1 to 0 and 0
to 1) will set a bit in the GPEDSn registers. The GPFENn registers use synchronous
edge detection. This means the input signal is sampled using the system clock and
then it is looking for a “100” pattern on the sampled signal. This has the effect of
suppressing glitches.
I know it's about interrupts. I just wonder if the same logic is used in the level registers.

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Re: RPi4B GPIO reading speed

Fri Jul 12, 2019 8:16 pm

From my understanding, the rate at which you can read a GPIO register is less than on previous models, correct?

As a test, can you time how long it takes to spin in a loop and read any register in the GPIO block 100,000 times and compare with a 3B+?
Rockets are loud.

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Re: RPi4B GPIO reading speed

Sat Jul 13, 2019 9:12 am

I haven't tried a 3B+, (only got interested in this after the 4 was released) but after your suggestion I'll get one and give it a try.

The read loop looks like this:

Code: Select all

GPIO_SET(P_FRAME);                      // start the frame

while(word < n_words)
    gpio_regs[7] = (1 << 18);           // set MR high
    //gpio_regs[7] = (1 << 18);
    *data++ = gpio_regs[13];
    gpio_regs[10] = (1 << 18);          // clear MR
    //gpio_regs[10] = (1 << 18);
    *data++ = gpio_regs[13];
    word += 2;

GPIO_CLR(P_FRAME);                      // end the frame
The FPGA presents a new word of data on GPIO 0-15 on every edge of the MR signal. It does so with a typical delay of 10ns.
The time measured between MR going high and then going low again, and MR going low and then high again is consistent and repeatable for every read in a burst of 2048 and is 264ns, the period on MR is 528ns (MR high to next MR high) . These times do not vary if you uncomment the commented lines of code or change the compiler optimisation.
changing the read lines to *data++ = *gpio_level; (where gipo_level points to gpio_regs[13]) makes no difference to the timing.


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Joined: Fri Jul 12, 2019 2:45 pm

Re: RPi4B GPIO reading speed

Sat Jul 13, 2019 9:57 am

I have a good enough answer to my problem !

I've never used Pi before (although I've eaten a few) and hadn't realised how the clock speed keeps changing.

Mine is idling at 600MHz and doesn't change when I run a test of 2048 reads.

If I run the test loop many times at some point the processor shifts gear and the MR period drops to 240ns.

This is good enough for me as it represents a data input rate of 16.66 Mbyte/s.

Thanks for help.


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